Final result checking for system with pre-verified cores
Provided are a system and method for generating final result checking for a test case. A test case is executed for a coherent memory system having a processor core. An event log is generated for the processor core. The event log is analyzed. The test case for the core is annotated with a checker for performing expected data checking for physical addresses modified by the processor core.
1. A method for generating final result checking for a test case, comprising:
executing a test case by a coherent memory system having a processor core;
generating an event log for the processor core in response to executing the test case;
filtering the event log to extract instruction information;
generating a checker from the instruction information;
annotating the test case with the checker for performing expected data checking for physical addresses modified by the processor core; and
executing the annotated test case by the coherent memory system, including performing the expected data checking for the physical addresses modified by the processor core.
2. The method of claim 1 , further comprising performing a result checking operation comprising:
reading by the checker a memory physical address in the event log; and
comparing the contents corresponding to the memory physical address with an expected value from the event log to validate circuit design functionality.
3. The method of claim 1 , further comprising:
executing the annotated test case on a software release.
4. The method of claim 1 , further comprising:
executing the annotated test case on a register transfer level (RTL) logic release.
5. The method of claim 1 , wherein the test case is a system level verification test case.
6. The method of claim 1 , further comprising:
executing the annotated test case on silicon.
7. The method of claim 1 , wherein the event log comprises a plurality of event log records, each including a timestamp, a physical address, an updated memory content corresponding to the physical address, a core index, and a cluster index.
8. The method of claim 1 , further comprising filtering the event log, comprising:
filtering the extracted instruction information includes memory change instructions.
9. The method of claim 1 , wherein analyzing the event log comprises filtering the extracted information pertaining to a coherent memory region.
10. The method of claim 1 , wherein analyzing the event log comprises:
filtering redundant entries from the event log pertaining to a same physical address; and
retaining an entry with a most recent timestamp.
11. The method of claim 1 , wherein the processor core reads contents of a memory and performs final result checking for physical addresses modified by the processor core.
12. A method for generating final result checking for a test case, comprising:
executing a test case by a coherent memory system having a plurality of processor cores;
generating an event log for each processor core in response to executing the test case;
merging the event logs of the processor cores;
filtering the event logs to extract memory change instruction information;
selecting a processor core of the plurality of processor cores according to the merged event logs for performing the expected data checking;
generating a checker from the event logs;
annotating the test case with the checker for performing expected data checking for physical addresses modified by the selected processor core; and
executing the annotated test case by the coherent memory system, including performing the expected data checking.
13. The method of claim 12 , wherein the processor core of the plurality of processor cores is selected by sorting the database of event logs based on a timestamp to identify a core number of the processor core that initiated a most recent transaction.
14. The method of claim 12 , wherein the selected processor core reads contents of a memory and performs final result checking for physical addresses modified by the plurality of processor cores.
15. A verification system, comprising:
a processor core that executes a test case for a coherent memory system;
an event log analyzer that analyzes an event log generated for the processor core; and
a test case annotation module that annotates the test case with a checker for performing expected data checking for physical addresses modified by the processor core.
16. The verification system of claim 15 , wherein an event log filter filters collected information from the event log to extract information regarding memory change instructions.
17. The verification system of claim 15 , wherein the checker is generated in response to the analyzer analyzing the event log, and wherein the checker reads at least one physical address in the event log, and compares contents corresponding to the at least one physical address with an expected value in the event log.
18. The verification system of claim 15 , wherein the coherent memory system has a plurality of processor cores, wherein an event log is generated for each processor core, and wherein the verification system merges the event logs of the processor cores at a database; and selects a processor core of the plurality of processor cores according to the merged event logs for performing the expected data checking.
19. The verification system of claim 15 , wherein the annotated test case is executed on a register transfer level (RTL) logic release or silicon.
20. The verification system of claim 15 , wherein the test case is loaded on an on-chip or flash memory for reuse on silicon.