IP Library Granted Patent US 9,812,415
Granted Patent B2
US 9,812,415 · App. 14/506,423 · Granted Nov 7, 2017

Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices

Inventors: Matt E. Schwab (Boise, ID); David J. Corisis (Nampa, ID); J. Michael Brooks (Caldwell, ID)
Assignee: Micron Technology, Inc.
H01L24/03H01L21/56H01L23/49811H01L24/06H01L24/29H01L24/32H01L24/73H01L24/81H01L24/83H01L23/3128H01L23/49816H01L24/28H01L24/48H01L24/85H01L2224/0401H01L2224/11011H01L2224/13111H01L2224/1405H01L2224/16225H01L2224/2919H01L2224/29111H01L2224/32225H01L2224/48091H01L2224/48227H01L2224/48235H01L2224/73204H01L2224/73257H01L2224/73265H01L2224/81192H01L2224/81801H01L2224/81815H01L2224/83102H01L2224/83192H01L2224/83801H01L2224/85H01L2224/92125H01L2224/92247H01L2924/00014H01L2924/014H01L2924/0105H01L2924/01005H01L2924/01029H01L2924/0132H01L2924/0133H01L2924/01033H01L2924/01047H01L2924/01079H01L2924/01082H01L2924/0665H01L2924/10158H01L2924/10253H01L2924/14H01L2924/1579H01L2924/15174H01L2924/15184H01L2924/15311H01L2924/181H01L2924/3511
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Quick Facts
Patent No.
US 9,812,415
App. No.
14/506,423
Granted
Nov 7, 2017
Kind
B2
Abstract

Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed. In one embodiment, a method for forming a microelectronic device includes attaching a microelectronic die to a support member by forming an attachment feature on at least one of a back side of the microelectronic die and the support member. The attachment feature includes a volume of solder material. The method also includes contacting the attachment feature with the other of the microelectronic die and the support member, and reflowing the solder material to join the back side of the die and the support member via the attachment feature. In several embodiments, the attachment feature is not electrically connected to internal active structures of the die.

Claims (12)

1. A method for mounting a semiconductor device to a circuit board, the method comprising:

depositing a plurality of pre-formed solder balls on at least a portion of a device attach region of the circuit board;

juxtaposing a back side of the semiconductor device and the pre-formed solder balls;

forming a generally rigid connection between the back side of the semiconductor device and the circuit board by contacting the pre-formed solder balls with a conductive layer and reflowing the pre-formed solder balls and conductive layer to form a single, unitary connection structure, wherein the conductive layer covers all of the back side of the semiconductor device: and

forming a plurality of wire bonds between terminals at a front side of the semiconductor device and corresponding contacts on the circuit board after forming the generally rigid connection between the semiconductor device and the circuit board.

2. The method of claim 1 wherein forming a generally rigid connection between the back side of the semiconductor device and the circuit board comprises attaching the semiconductor device to the circuit board in a chip-on-board (COB) configuration.

3. The method of claim 1 wherein depositing a plurality of pre-formed solder balls on at least a portion of a device attach area comprises depositing solder balls composed of at least one of a SnAgCu, SnAg, and SnAu solder material.

4. The method of claim 1 , further comprising depositing a non-conductive fill material in one or more interstitial spaces between the semiconductor device and the circuit board after forming the generally rigid connection.

5. The method of claim 1 , further comprising encapsulating the semiconductor device, the wire bonds, and at least a portion of the circuit board after forming the wire bonds.

6. The method of claim 1 wherein depositing a plurality of pre-formed solder balls on at least a portion of a device attach area comprises depositing solder balls composed of lead-free solder material.

7. The method of claim 1 , further comprising depositing a conductive layer on the back side of the semiconductor device, the conductive layer having a plurality of conductive pads arranged in a pattern corresponding at least in part to the arrangement of solder balls.

8. The method of claim 1 wherein forming a generally rigid connection between the back side of the semiconductor device and the circuit board comprises forming a connection structure that does not transmit signals between the semiconductor device and the circuit board.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
Continuity (3)
Division 13155203 · Jun 7, 2011
Division 11685621 · Mar 13, 2007
Related Publication 20150021769A1 · Jan 22, 2015