Vertical gallium nitride power device with breakdown voltage control
View Patent ↗A method for fabricating a vertical GaN power device includes providing a first GaN material having a first conductivity type and forming a second GaN material having a second conductivity type and coupled to the first GaN material to create a junction. The method further includes implanting ions through the second GaN material and into a first portion of the first GaN material to increase a doping concentration of the first conductivity type. The first portion of the junction is characterized by a reduced breakdown voltage relative to a breakdown voltage of a second portion of the junction.
1. A method for fabricating a vertical GaN power device, the method comprising:
providing a first GaN material having a first conductivity type;
forming a second GaN material having a second conductivity type and coupled to the first GaN material to create a p-n junction; and
implanting ions through the second GaN material and into a first portion of the first GaN material to form an implanted region extending from within the first GaN material across the p-n junction into the second GaN material, wherein the implanted region spans a first portion of the p-n junction, such that the p-n junction extends from within the implanted region across a boundary of the implanted region into a second portion of the p-n junction,
wherein the first portion of the p-n junction has a breakdown voltage which is less than a breakdown voltage of the second portion of the p-n junction.
2. The method of claim 1 , further comprising forming the first portion of the p-n junction such that the second portion of the p-n junction is between an edge of the p-n junction and the first portion of the p-n junction.
3. The method of claim 1 , wherein the first conductivity type is n-type.
4. The method of claim 3 , wherein with the implanted ions comprise silicon.
5. The method of claim 1 , wherein the vertical GaN power device comprises a diode.
6. The method of claim 5 , wherein the diode comprises a Schottky barrier diode.
7. The method of claim 1 , wherein the vertical GaN power device comprises a junction field-effect transistor (JFET).
8. The method of claim 1 , wherein a first dopant concentration of the first GaN material in the implanted region is higher than a second dopant concentration of the first GaN material in the second portion of the p-n junction.
9. The method of claim 1 , further comprising forming one or more edge termination structures.
10. The method of claim 9 , wherein at least one of the termination structures comprises a junction termination region comprising
a plurality of junction termination elements, each having a different dopant density.
11. The method of claim 10 , wherein those junction termination elements closer to the implanted region have a higher dopant density than those junction termination elements farther from the implanted region.
12. The method of claim 10 , further comprising forming an isolation element in the edge termination structure.
13. The method of claim 12 , wherein the junction termination elements are between the isolation element and the implanted region.
14. The method of claim 9 , wherein at least one of the termination structures comprises a junction termination region comprising a guard ring at least partially circumscribing the p-n junction.