Low-cost semiconductor device manufacturing method
View Patent ↗Provided are a low-cost semiconductor device manufacturing method and a semiconductor device made using the method. The method includes forming multiple body regions in a semiconductor substrate, forming multiple gate insulating layers and multiple gate electrodes in the body region; implementing a blanket ion implantation in an entire surface of the substrate to form a low concentration doping region (LDD region) in the body region without a mask, forming a spacer at a side wall of the gate electrode, and implementing a high concentration ion implantation to form a high concentration source region and a high concentration drain region around the LDD region. According to the examples, devices have favorable electrical characteristics and at the same time, manufacturing costs are reduced. Since, when forming high concentration source region and drain regions, tilt and rotation co-implants are applied, an LDD masking step is potentially omitted.
1. A method of manufacturing a semiconductor device, the method comprising:
preparing a first region and a second region in a semiconductor substrate;
forming a first body region having a high concentration of dopant in the first region to form a high-threshold voltage device;
forming a second body region having a low concentration of dopant in the second region to form a low-threshold voltage device;
forming a gate electrode over the first body region and the second body region;
blanket implanting dopants of a second conductivity type into the first body and second body region to form low-doped drain (LDD) regions;
forming a spacer next to the gate electrode; and
source-drain implanting a second conductivity type of dopant to form a low-resistance source/drain region and low-doped extension that extends under the spacer,
wherein the source-drain implantation comprises tilted and rotated implantation, and
wherein the blanket implantation and the source-drain implantation are sufficient to compensate for enough of the first body region of the high-threshold voltage device, to ensure a low-resistance link between the source/drain region and a channel region.
2. The method of claim 1 ,
wherein the blanket implantation has a low dose ranging from 1E11 to 5E13 ions cm 2 .
3. The method of claim 1 ,
wherein the source-drain implantation further comprises performing substantially perpendicular implantation of a first dose with respect to a surface of the semiconductor substrate.
4. The method of claim 1 , wherein the tilted and rotated implantation comprises a second dose lower than the first dose at a tilted angle with respect to the surface of the semiconductor substrate so as to form the low-resistance link under the spacer.
5. The method of claim 4 ,
wherein the first dose ranges from 5E14 to 1E16 ions cm −2 and the second dose ranges from 1E12 to 1E14 ions cm −2 .
6. The method of claim 1 ,
wherein the blanket implantation skips all masking operations when forming the low-doped drain region.
7. A method of manufacturing a semiconductor device, the method comprising:
preparing a first region and a second region in a semiconductor substrate;
forming a first body region having a high concentration of dopant in the first region to form a high-threshold voltage device;
forming a second body region having a low concentration of dopant in the second region to form a low-threshold voltage device;
forming a gate electrode over the first body region and the second body region;
blanket implanting dopants of a second conductivity type into the first body and second body region to form low-doped drain (LDD) regions;
forming a spacer next to the gate electrode; and
source-drain implanting a second conductivity type of dopant to form a low-resistance source/drain region and low-doped extension that extends under the spacer.
8. The method of claim 7 , wherein the source-drain implantation comprises tilted and rotated implantation.
9. The method of claim 8 , wherein the tilted and rotated implantation comprises a second dose lower than the first dose at a tilted angle with respect to the surface of the semiconductor substrate so as to form the low-resistance link under the spacer.
10. The method of claim 9 ,
wherein the first dose ranges from 5E14 to 1E16 ions cm −2 and the second dose ranges from 1E12 to 1E14 ions cm −2 .
11. The method of claim 7 , wherein the blanket implantation and the source-drain implantation are sufficient to compensate for enough of the first body region of the high-threshold voltage device, to ensure a low-resistance link between the source/drain region and a channel region.
12. The method of claim 7 ,
wherein the blanket implantation has a low dose ranging from 1E11 to 5E13 ions cm 2 .
13. The method of claim 7 ,
wherein the source-drain implantation further comprises performing substantially perpendicular implantation of a first dose with respect to a surface of the semiconductor substrate.
14. The method of claim 7 ,
wherein the blanket implantation skips all masking operations when forming the low-doped drain region.