IP Library Granted Patent US 9,312,208
Granted Patent B2
US 9,312,208 · App. 14/521,456 · Granted Apr 12, 2016

Through silicon via structure

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,312,208
App. No.
14/521,456
Granted
Apr 12, 2016
Kind
B2
Abstract

A through silicon via structure is disclosed. The through silicon via includes: a substrate; a first dielectric layer disposed on the substrate and having a plurality of first openings, in which a bottom of the plurality of first openings is located lower than an original surface of the substrate; a via hole disposed through the first dielectric layer and the substrate, in which the via hole not overlapping for all of the plurality of first openings; a second dielectric layer disposed within the plurality of first openings and on a sidewall of the via hole while filling the plurality of first openings; and a conductive material layer disposed within the via hole having the second dielectric layer on the sidewall of the via hole, thereby forming a through silicon via.

Claims (9)

1. A through silicon via structure, comprising:

a substrate;

a first dielectric layer disposed on the substrate and having a plurality of first openings, wherein a bottom of the plurality of first openings is located lower than an original surface of the substrate;

a via hole disposed through the first dielectric layer and the substrate, wherein the via hole not overlapping for all of the plurality of first openings;

a second dielectric layer disposed within the plurality of first openings and on a sidewall of the via hole while filling the plurality of first openings completely; and

a conductive material layer disposed within the via hole having the second dielectric layer on the sidewall of the via hole, thereby forming a through silicon via, wherein the second dielectric layer comprises a plurality of second openings corresponding to the plurality of first openings, and the conductive material layer is further disposed within the plurality of second openings to form a plurality of dummy through silicon vias.

2. The through silicon via structure according to claim 1 , further comprising a barrier layer between the conductive material layer and the second dielectric layer.

3. The through silicon via structure according to claim 1 , wherein a diameter of the through silicon via and a diameter of one of the plurality of dummy through silicon vias are the same.

4. The through silicon via structure according to claim 1 , wherein the substrate comprises a semiconductor element.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2021
From: UNITED MICROELECTRONICS CORPORATION
To: MARLIN SEMICONDUCTOR LIMITED
Reel/Frame 056991/0292 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 22, 2014
From: CHEN, HSIN-YU; CHENG, HOME-BEEN; TSAI, YU-HAN; YANG, CHING-LI
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 034011/0697 →