IP Library Granted Patent US 9,666,930
Granted Patent B2
US 9,666,930 · App. 14/521,620 · Granted May 30, 2017

Interface between a semiconductor die and a waveguide, where the interface is covered by a molding compound

Inventors: Jinbang Tang (Chandler, AZ); Neil T. Tracht (Paradise Valley, AZ)
Assignee: NXP USA, INC.
H01P5/107H01L23/66H01P11/003H01L23/3121H01L2224/18H01L2924/0002
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Quick Facts
Patent No.
US 9,666,930
App. No.
14/521,620
Granted
May 30, 2017
Kind
B2
Abstract

The embodiments described herein provide for the formation of circuit waveguide interfaces during a wafer-scale die packaging (WSDP) process. Specifically, during the packaging process singulated die are arranged on a wafer-like panel and covered with molding compound that will provide the bodies of the packages. A circuit waveguide interface is formed in the molding compound and subsequent metallization layers. This circuit waveguide interface can include an array of first conductors arranged in the molding compound, and a reflector interface and excitation element formed during metallization.

Claims (55)

1. A semiconductor device comprising:

a semiconductor die including an integrated circuit, the semiconductor die having a first side and a second side;

a molding compound that covers the semiconductor die, the molding compound having a first side and a second side, the molding compound first side corresponding to the semiconductor die first side, and the molding compound second side corresponding to the semiconductor die second side;

a first array of conductors, the first array of conductors extending from the molding compound first side to the molding compound second side, the first array of conductors arranged in the molding compound to define a first waveguide interface perimeter surrounding a first waveguide interface interior;

an excitation element formed at the molding compound first side, the excitation element coupled to the semiconductor die and extending past the first waveguide interface perimeter into the first waveguide interface interior; and

a plurality of package pads formed at the molding compound first side.

2. The semiconductor device of claim 1 further comprising:

a reflector interface formed at the molding compound first side, the reflector interface substantially extending around and overlapping the first waveguide interface perimeter.

3. The semiconductor device of claim 1 further comprising a conductive layer formed at the molding compound second side.

4. The semiconductor device of claim 1 further comprising:

a circuit board having a first side and a second side; and

a second array of conductors, the second array of conductors extending from the circuit board first side to the circuit board second side, the second array of conductors arranged in the circuit board to define a second waveguide interface perimeter surrounding a second waveguide interface interior.

5. The semiconductor device of claim 4 further comprising:

an interface structure formed at the circuit board first side, the interface structure substantially extending around and overlapping the second waveguide interface perimeter; and

a coupling structure formed at the circuit board second side, the coupling structure substantially extending around and overlapping the second waveguide interface perimeter, the coupling structure defining a coupling slot over the second waveguide interface interior.

6. The semiconductor device of claim 5 wherein the coupling structure is physically coupled to a reflector interface with an array of conductive balls.

7. The semiconductor device of claim 5 wherein the interface structure is configured to physically couple to a waveguide.

8. The semiconductor device of claim 1 wherein the first array of conductors comprises vias in the molding compound filled with conductive material.

9. The semiconductor device of claim 1 wherein the first array of conductors comprises conductive studs that are covered with the molding compound.

10. A semiconductor device comprising:

a semiconductor die including an integrated circuit, the semiconductor die having an active side with die bonding pads and an inactive side opposite the active side;

a molding compound that covers the semiconductor die, the molding compound having a first side and a second side, the molding compound first side corresponding to the semiconductor die active side, and the molding compound second side corresponding to the semiconductor die inactive side;

a first array of conductors, the first array of conductors extending from the molding compound first side to the molding compound second side, the first array of conductors arranged in the molding compound to define a first waveguide interface perimeter surrounding a first waveguide interface interior;

a reflector interface formed at the molding compound first side, the reflector interface substantially extending around and overlapping the first waveguide interface perimeter;

an excitation element formed at the molding compound first side, the excitation element coupled to the semiconductor die and extending past the first waveguide interface perimeter to the first waveguide interface interior;

a plurality of package pads formed at the molding compound first side;

a ball array coupled to the plurality of package pads;

a conductive layer formed over the molding compound second side;

a circuit board having a first side and a second side;

a second array of conductors, the second array of conductors extending from the circuit board first side to the circuit board second side, the second array of conductors arranged in the circuit board to define a second waveguide interface perimeter surrounding a second waveguide interface interior;

an interface structure formed at the circuit board first side, the interface structure substantially extending around and overlapping the second waveguide interface perimeter;

a coupling structure formed at the circuit board second side, the coupling structure substantially extending around and overlapping the second waveguide interface perimeter, the coupling structure defining a coupling slot over the second waveguide interface interior; and

conductive material to couple the coupling structure to the reflector interface.

11. A method for forming a semiconductor device, the method comprising:

providing a semiconductor die including an integrated circuit, the semiconductor die having a first side and a second side;

covering the semiconductor die in molding compound, the molding compound having a first side and a second side, the molding compound first side corresponding to the semiconductor die first side, and the molding compound second side corresponding to the semiconductor die second side;

forming a first array of conductors in the molding compound, the first array of conductors extending from the molding compound first side to the molding compound second side, the first array of conductors arranged in the molding compound to define a first waveguide interface perimeter surrounding a first waveguide interface interior;

forming an excitation element at the molding compound first side, the excitation element coupled to the semiconductor die and extending past the first waveguide interface perimeter to the first waveguide interface interior.

12. The method of claim 11 wherein the step of forming the first array of conductors in the molding compound comprises:

arranging a plurality of conductive studs; and

covering the conductive studs with the molding compound during the step of covering the semiconductor die in the molding compound.

13. The method of claim 11 further comprising:

forming a reflector interface at the molding compound first side, the reflector interface substantially extending around and overlapping the first waveguide interface perimeter.

14. The method of claim 11 further comprising forming a conductive layer at the molding compound second side.

15. The method of claim 11 further comprising:

providing a circuit board having a first side and a second side; and

forming a second array of conductors, the second array of conductors extending from the circuit board first side to the circuit board second side, the second array of conductors arranged in the circuit board to define a second waveguide interface perimeter surrounding a second waveguide interface interior.

16. The method of claim 15 further comprising:

forming an interface structure at the circuit board first side, the interface structure substantially extending around and overlapping the second waveguide interface perimeter; and

forming a coupling structure at the circuit board second side, the coupling structure substantially extending around and overlapping the second waveguide interface perimeter, the coupling structure defining a coupling slot over the second waveguide interface interior.

17. The method of claim 16 further comprising physically coupling the coupling structure to a reflector interface with an array of conductive balls.

18. The method of claim 16 further comprising physically coupling the interface structure to a waveguide.

19. The method of claim 11 wherein the step of forming the first array of conductors in the molding compound comprises:

forming vias in the molding compound; and

filling the vias with conductive material.

Assignments (11)
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040626 FRAME: 0683. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME EFFECTIVE NOVEMBER 7, 2016. Recorded Jan 12, 2017
From: NXP SEMICONDUCTORS USA, INC. (MERGED INTO); FREESCALE SEMICONDUCTOR, INC. (UNDER)
To: NXP USA, INC.
Reel/Frame 041414/0883 →
CHANGE OF NAME Recorded Nov 16, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040626/0683 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037444/0444 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037444/0535 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037358/0001 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Feb 18, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 035033/0001 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Feb 18, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 035034/0019 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Feb 18, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 035033/0923 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 23, 2014
From: TANG, JINBANG; TRACHT, NEIL T.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 034017/0001 →
Continuity (1)
Related Publication 20160118705A1 · Apr 28, 2016