IP Library Granted Patent US 9,269,645
Granted Patent B1
US 9,269,645 · App. 14/521,893 · Granted Feb 23, 2016

Fan-out wafer level package

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Quick Facts
Patent No.
US 9,269,645
App. No.
14/521,893
Granted
Feb 23, 2016
Kind
B1
Abstract

A fan-out wafer level package is provided. The fan-out wafer level package includes a semiconductor element, a molding compound, a first fan-out structure, a conductive heat spreader, and a plurality of solder balls. The semiconductor element includes a plurality of bonding pads. The molding compound covers the semiconductor element. The first fan-out structure is formed on the semiconductor element, wherein the first fan-out structure has a plurality of fan-out contacts electrically connected to the bonding pads. The conductive heat spreader is formed on the first fan-out structure, wherein the conductive heat spreader has a plurality of through holes filled with a conductive material. The solder balls are formed on the conductive heat spreader, wherein the solder balls are electrically connected to the first fan-out structure via the through holes filled with the conductive material.

Claims (26)

1. A fan-out wafer level package, comprising:

a semiconductor element comprising a plurality of bonding pads;

a molding compound covering the semiconductor element;

a first fan-out structure formed on the semiconductor element, wherein the first fan-out structure has a plurality of fan-out contacts electrically connected to the bonding pads;

a conductive heat spreader formed on the first fan-out structure, wherein the conductive heat spreader has a plurality of through holes filled with a conductive material; and

a plurality of solder balls formed on the conductive heat spreader, wherein the solder balls are electrically connected to the first fan-out structure via the through holes filled with the conductive material.

2. The fan-out wafer level package according to claim 1 , wherein the conductive heat spreader comprises a plurality of insulation layers formed between sidewalls of the through holes and the conductive material.

3. The fan-out wafer level package according to claim 1 , wherein the conductive heat spreader comprises a conductive layer, wherein the conductive layer comprises at least one of silicon, copper, or aluminum.

4. The fan-out wafer level package according to claim 3 , wherein the conductive heat spreader further comprises two oxide layers formed on two opposite surfaces of the conductive layer, respectively.

5. The fan-out wafer level package according to claim 1 , wherein the first fan-out structure comprises:

an organic dielectric layer; and

a plurality of fan-out wires formed in the organic dielectric layer.

6. The fan-out wafer level package according to claim 5 , wherein the fan-out wires are electrically connected to the fan-out contacts of the first fan-out structure.

7. The fan-out wafer level package according to claim 5 , wherein the fan-out wires have a first line width, the through holes filled with the conductive material have a second line width larger than the first line width.

8. The fan-out wafer level package according to claim 5 , wherein the first fan-out structure further comprises:

at least a passive component formed in the organic dielectric layer.

9. The fan-out wafer level package according to claim 1 , further comprising:

a second fan-out structure formed on the conductive heat spreader, wherein the first fan-out structure is electrically connected to the second fan-out structure.

10. The fan-out wafer level package according to claim 9 , wherein the second fan-out structure is electrically connected to the solder balls.

11. The fan-out wafer level package according to claim 9 , further comprising:

a third fan-out structure formed on the conductive heat spreader, wherein the second fan-out structure and the third fan-out structure are formed on two opposite surfaces of the conductive heat spreader, respectively, and the third fan-out structure is electrically connected to the second fan-out structure.

12. The fan-out wafer level package according to claim 1 , wherein the bonding pads comprise aluminum.

13. The fan-out wafer level package according to claim 1 , wherein the solder balls are formed as a ball grid array (BGA).

14. The fan-out wafer level package according to claim 1 , further comprising:

at least a through molding via formed in the molding compound, wherein the through molding via is electrically connected to at least one of the solder balls.

15. The fan-out wafer level package according to claim 1 , wherein the semiconductor element further comprises a dielectric structure formed on the bonding pads.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2021
From: UNITED MICROELECTRONICS CORPORATION
To: MARLIN SEMICONDUCTOR LIMITED
Reel/Frame 056991/0292 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 23, 2014
From: LIN, CHU-FU; KUO, CHIEN-LI; CHEN, KUO-MING
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 034019/0773 →