System for reducing power consumption of integrated circuit
A method for reducing dynamic power consumption of an integrated circuit design having flip-flops with an EDA tool that initiates clock gating by gating a clock signal received by the flip-flops. A first set of positive-edge triggered flip-flops and a second set of negative-edge triggered flip-flops, and a first set of OR-type clock gating cells and a second set of AND-type clock gating cells are selected from a technology library. The OR-type clock gating cells are connected to clock input terminals of the first set of positive-edge triggered flip-flops and the AND-type clock gating cells to clock terminals of the second set of negative-edge triggered flip-flops.
1. A method for making an integrated circuit, comprising:
modifying an initial integrated circuit design to reduce dynamic power consumption of the design using an electronic design automation (EDA) tool, wherein the EDA tool includes a memory for storing the initial design and a technology library, and a processor coupled to the memory, wherein the initial design includes a plurality of flip-flops, and wherein modifying the initial design comprises:
identifying, by the processor, a first set of positive-edge triggered flip-flops and a second set of negative-edge triggered flip-flops of the plurality of flip-flops;
selecting, from the technology library, a first set of OR-type clock gating cells and a second set of AND-type clock gating cells;
connecting the first set of OR-type clock gating cells to clock terminals of corresponding ones of the first set of positive-edge triggered flip-flops, and the second set of AND-type clock gating cells to clock terminals of corresponding ones of the second set of negative-edge triggered flip-flops;
saving the modified initial design in the memory; and
fabricating the integrated circuit using the modified initial design.
2. The method of claim 1 , further comprising receiving an external clock signal and generating first and inverted first clock gating signals by each OR-type clock gating cell of the first set of OR-type clock gating cells and receiving the external clock signal and generating second and inverted second clock gating signals by each AND-type clock gating cell of the second set of AND-type clock gating cells.
3. The method of claim 2 , wherein a positive-edge triggered flip-flop includes:
a first pass gate having an input terminal for receiving an external data input signal, first and second clock input terminals for receiving the first and inverted first clock gating signals, respectively, from a corresponding one of the OR-type clock gating cells, and an output terminal for transmitting the external data input signal;
a master latch having a data input terminal connected to the output terminal of the first pass gate for receiving the external data input signal, first and second clock input terminals for receiving the inverted first and first clock gating signals, respectively, from a corresponding one of the OR-type clock gating cells, and an output terminal for outputting the external data input signal when the external clock signal is at logic low state;
a second pass gate having an input terminal connected to the output terminal of the master latch for receiving the external data input signal, first and second clock input terminals for receiving the inverted first and first clock gating signals, respectively, from one of the corresponding OR-type clock gating cells, and an output terminal for transmitting the external data input signal; and
a slave latch having a data input terminal connected to the output terminal of the second pass gate for receiving the external data input signal, and an output terminal for outputting the external data input signal when the external clock signal is in a logic high state.
4. The method of claim 3 , further comprising gating the external data input signal by the first pass gate when the first and inverted first clock gating signals are at logic high and logic low states, respectively, and enabling transmission of the external data input signal by the first pass gate when the first and inverted first clock gating signals are at logic low and logic high states, respectively.
5. The method of claim 4 , further comprising setting the master latch in a latch mode when the first and inverted first clock gating signals are at logic high and logic low states, respectively, and a transparent mode when the first and inverted first clock gating signals are at logic low and logic high states, respectively.
6. The method of claim 2 , wherein a negative-edge triggered flip-flop includes:
a first pass gate having an input terminal for receiving an external data input signal, first and second clock input terminals for receiving the inverted second and second clock gating signals, respectively, from one of the corresponding AND-type clock gating cells, and an output terminal for transmitting the external data input signal;
a master latch having a data input terminal connected to the output terminal of the first pass gate for receiving the external data input signal, first and second clock input terminals for receiving the second and inverted second clock gating signals, respectively, from a corresponding one of the AND-type clock gating cells, and an output terminal for outputting the external data input signal when the external clock signal is at logic high state;
a second pass gate having an input terminal connected to the output terminal of the master latch for receiving the external data input signal, first and second clock input terminals for receiving the second and inverted second clock gating signals, respectively, from a corresponding one of the AND-type clock gating cells, and an output terminal for transmitting the external data input signal; and
a slave latch having a data input terminal connected to the output terminal of the second pass gate for receiving the external data input signal, and an output terminal for outputting the external data input signal when the external clock signal is at logic low state.
7. The method of claim 6 , further comprising gating the external data input signal by the first pass gate when the second and inverted second clock gating signals are at logic low and logic high states, respectively, and enabling transmission of the external data input signal by the first pass gate when the second and inverted second clock gating signals are at logic high and logic low states, respectively.
8. The method of claim 7 , further comprising setting the master latch in a latch mode when the second and inverted second clock gating signals are at logic low and logic high states, respectively, and a transparent mode when the second and inverted second clock gating signals are at logic high and logic low states, respectively.