Integrated circuit devices with counter-doped conductive gates
Integrated circuit devices with counter-doped conductive gates. The devices have a semiconductor substrate that has a substrate surface. The devices also have a first well of a first conductivity type, a source of a second conductivity type, and a drain of the second conductivity type. A channel extends between the source and the drain. A conductive gate extends across the channel. The conductive gate includes a first gate region and a second gate region of the second conductivity type and a third gate region of the first conductivity type. The third gate region extends between the first and second gate regions. The devices further include a gate dielectric that extends between the conductive gate and the substrate and also include a silicide region in electrical communication with the first, second, and third gate regions. The methods include methods of manufacturing the devices.
1. An integrated circuit device, comprising:
a semiconductor substrate having a substrate surface;
a well of a first conductivity type extending from the substrate surface;
a source of a second conductivity type, which is different from the first conductivity type, formed within the well and extending from the substrate surface;
a drain of the second conductivity type formed within the well and extending from the substrate surface;
a channel formed within the well, the channel extending along the substrate surface and electrically separating the source and the drain;
a conductive gate extending across the substrate surface and along the channel between the source and the drain and comprising
(i) a first gate region of the second conductivity type, wherein the first gate region comprises a second dopant of the second conductivity type,
(ii) a second gate region of the second conductivity type, wherein the second gate region comprises the second dopant of the second conductivity type, and
(iii) a third gate region of the first conductivity type, wherein the third gate region extends between the first gate region and the second gate region, wherein the third gate region comprises a first dopant of the first conductivity type, and further wherein a concentration of the first dopant within the third gate region is at least 110% of a concentration of the second dopant within the first gate region and within the second gate region;
a gate dielectric extending between and electrically isolating the conductive gate and the substrate surface; and
a silicide region in electrical communication with the first gate region, the second gate region, and the third gate region.
2. The device of claim 1 , wherein the first gate region, the second gate region, the third gate region, and the silicide region are formed from a polycrystalline silicon body.
3. The device of claim 1 , wherein the first gate region, the second gate region, and the third gate region extend between the silicide region and the gate dielectric.
4. The device of claim 1 , wherein the third gate region is in direct electrical contact with the first gate region and with the second gate region.
5. The device of claim 1 , wherein the first gate region forms a source-proximal edge of the conductive gate that extends above at least a portion of the source, wherein the second gate region forms a drain-proximal edge of the conductive gate that extends above at least a portion of the drain, and further wherein the third gate region extends across the channel and between the source and the drain.
6. The device of claim 1 , wherein a trench region containing a trench dielectric extends from the substrate surface and around the well to form a portion of a boundary of the well.
7. The device of claim 1 , wherein the first conductivity type is n-type and the second conductivity type is p-type.
8. The device of claim 1 , wherein the gate dielectric is formed from a single, continuous layer of dielectric material that extends between the substrate surface and the first gate region, the second gate region, and the third gate region.