Method for creating a reliable phase-locked loop in a ruggedized or harsh environment
View Patent ↗A phase-locked loop (PLL) circuit system includes first, second, and third PLL circuits, first, second, and third multiplexer circuits coupled to the first, second, and third PLL circuits, and a majority voter circuit coupled to the first, second, and third PLL circuits, wherein the PLL circuit system provides a glitch-free output clock signal by selecting a locked PLL circuit. Each PLL circuit includes a first input for receiving a reference clock signal; a second input for receiving a feedback clock signal; a first output for providing an output clock signal; a second output for providing a lock signal; and a return path coupled between the first output and the second input. The return path can be a direct connection or a logic circuit. Each multiplexer circuit includes three lock inputs, a first clock input, a second clock input, a defeat input, and a clock output.
1. A phase-locked loop (PLL) circuit system comprising:
first, second, and third PLL circuits;
first, second, and third multiplexer circuits coupled to the first, second, and third PLL circuits, and
a majority voter circuit coupled to the first, second, and third PLL circuits,
wherein the PLL circuit system provides a glitch-free output clock signal by selecting a locked PLL circuit, and
wherein each multiplexer circuit comprises three lock inputs, a first clock input, a second clock input, a defeat input, and a clock output.
2. The PLL circuit system of claim 1 wherein each PLL circuit comprises:
a first input for receiving a reference clock signal;
a second input for receiving a feedback clock signal;
a first output for providing an output clock signal;
a second output for providing a lock signal; and
a return path coupled between the first output and the second input.
3. The PLL circuit system of claim 2 wherein the return path comprises a direct connection.
4. The PLL circuit system of claim 2 wherein the return path comprises a logic circuit.
5. The PLL circuit system of claim 1 wherein each multiplexer circuit comprises a majority voter circuit coupled to the three lock inputs.
6. The PLL circuit system of claim 1 wherein each multiplexer circuit comprises a multiplexer coupled to the second clock input and the defeat input.
7. The PLL circuit system of claim 1 wherein each multiplexer circuit comprises a logic circuit coupled to the first clock input.
8. The PLL circuit system of claim 1 wherein each multiplexer circuit comprises a logic circuit coupled to the clock output.
9. The PLL circuit system of claim 1 wherein the majority voter circuit provides the glitch-free output clock signal.
10. A PLL circuit system comprising:
N PLL circuits;
N multiplexer circuits coupled to the N PLL circuits, and
a majority voter circuit coupled to the N PLL circuits,
wherein N is an integer greater than two,
wherein the PLL circuit system provides a glitch-free output clock signal by selecting a locked PLL circuit, and
wherein each multiplexer circuit comprises N lock inputs, a first clock input, a second clock input, a defeat input, and a clock output.
11. The PLL circuit system of claim 10 wherein each PLL circuit comprises:
a first input for receiving a reference clock signal;
a second input for receiving a feedback clock signal;
a first output for providing an output clock signal;
a second output for providing a lock signal; and
a return path coupled between the first output and the second input.
12. The PLL circuit system of claim 11 wherein the return path comprises a direct connection.
13. The PLL circuit system of claim 11 wherein the return path comprises a logic circuit.
14. A method of providing a glitch-free output clock signal in a PLL circuit system, the method comprising:
providing N PLL circuits;
coupling N multiplexer circuits to the N PLL circuits; and
selecting a locked PLL circuit with a majority voter circuit so that a glitch-free output clock signal is provided,
wherein N is an integer greater than two, and
wherein each multiplexer circuit comprises N lock inputs, a first clock input, a second clock input, a defeat input, and a clock output.
15. The method of claim 14 , wherein each PLL circuit comprises:
a first input for receiving a reference clock signal;
a second input for receiving a feedback clock signal;
a first output for providing an output clock signal;
a second output for providing a lock signal; and
a return path coupled between the first output and the second input.
16. The method of claim 15 , wherein the return path comprises a direct connection.
17. The method of claim 15 , wherein the return path comprises a logic circuit.