IP Library Granted Patent US 9,753,058
Granted Patent B2
US 9,753,058 · App. 14/529,033 · Granted Sep 5, 2017

Wiring board for testing loaded printed circuit board

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Quick Facts
Patent No.
US 9,753,058
App. No.
14/529,033
Granted
Sep 5, 2017
Kind
B2
Abstract

A wiring board for transmission of test signals between test point locations on a circuit board under test and an external analyzer having compliant contacts making electrical contact with a pad positioned on a conductive surface circuit layer having a trace extending to a second pad having a hole for receipt of an interface pin having a swaged head electrically connected to the external analyzer.

Claims (18)

1. A wiring board for transmission of test signals between test point locations on a circuit board under test and an external test analyzer comprising:

a single non-conductive board having a conductive circuit layer positioned on a top surface, the conductive circuit layer having a conductive first pad without a hole in the single non-conductive board and a conductive trace extending to a conductive second pad positioned around a hole extending through the single non-conductive board for receipt of an interface pin extending through the single non-conductive board; and

a compliant contact making electrical contact with the test point locations and the conductive first pad of the circuit layer.

2. The wiring board of claim 1 , wherein there are multiple conductive circuits layered on top of one another on the single non-conductive board.

3. The wiring board of claim 2 , wherein there is a compliant contact and an interface pin for each conductive circuit.

4. The wiring board of claim 1 , wherein the conductive second pad is a via.

5. The wiring board of claim 4 , wherein the interface pin extends through the via.

6. The wiring board of claim 4 , wherein a short headless pin extends through the via for the sole purpose of connecting the conductive second pad on one layer to another layer.

7. The wiring board of claim 4 , wherein the via has at least one flap around an opening which engages the interface pin.

8. The wiring board of claim 6 , wherein vias on successive layers have at least one flap rotated with respect to adjacent layers.

9. The wiring board of claim 1 , wherein the interface pin has a smooth round portion for contacting the conductive second pad at the middle or end of a trace.

10. The wiring board of claim 1 , wherein the conductive second pad is a via.

11. The wiring board of claim 1 , wherein the interface pin has a swaged or crimped feature for mechanical retention.

12. The wiring board of claim 1 , wherein the interface pin is piano or music wire.

13. The wiring board of claim 1 , further having a spare interface pin extending from a bottom of the wiring board which is wired to a rework receptacle.

14. The wiring board of claim 1 , further having a replacement interface pin extending from a bottom of the wiring board which is wired to a short pin when an offset of the interface pin is too large to tilt or bend into a normal position.

15. The wiring board of claim 1 , further comprising a probe socket extending through the non-conductive board for repair purposes or for the support of special purpose test probes.

16. The wiring board of claim 1 , wherein height of the test probes are controlled by a depth of a counter bore in a top plate so that the height is set for optimal compression when testing solder mask defined (SMD) lands or component leads of varying heights.

Assignments (6)
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS, RECORDED AT REEL 047185, FRAME 0624 Recorded Mar 7, 2024
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS AGENT
To: XCERRA CORPORATION
Reel/Frame 066762/0811 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT STATEMENT THAT THIS DOCUMENT SERVES AS AN OATH/DECLARATION PREVIOUSLY RECORDED ON REEL 047185 FRAME 0628. ASSIGNOR(S) HEREBY CONFIRMS THE PATENT SECURITY AGREEMENT. Recorded Nov 28, 2018
From: XCERRA CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 047675/0354 →
PATENT SECURITY AGREEMENT Recorded Oct 2, 2018
From: XCERRA CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 047185/0624 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 7261561 AND REPLACE WITH PATENT NUMBER 7231561 PREVIOUSLY RECORDED ON REEL 034660 FRAME 0188. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT. Recorded Feb 11, 2016
From: XCERRA CORPORATION; EVERETT CHARLES TECHNOLOGIES LLC
To: SILICON VALLEY BANK, AS ADMINISTRATIVE AGENT
Reel/Frame 037824/0372 →
SECURITY AGREEMENT Recorded Dec 18, 2014
From: XCERRA CORPORATION; EVERETT CHARLES TECHNOLOGIES LLC
To: SILICON VALLEY BANK, AS ADMINISTRATIVE AGENT
Reel/Frame 034660/0188 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 7, 2014
From: SWART, MARK A.; SNYDER, KENNETH R.; KOOLIS, STEPHEN J.; TACKETT, DOUGLAS W.
To: XCERRA CORPORATION
Reel/Frame 034127/0163 →