IP Library Granted Patent US 9,472,758
Granted Patent B2
US 9,472,758 · App. 14/538,763 · Granted Oct 18, 2016

High endurance non-volatile storage

Inventors: Zhida Lan (San Jose, CA); Abhijit Bandyopadhyay (San Jose, CA); Christopher Petti (Mountain View, CA); Li Xiao (San Jose, CA); Girish Nagavarapu (Mountain View, CA)
Assignee: SANDISK TECHNOLOGIES LLC
H01L45/16G11C13/0069H01L27/2481G11C13/0004G11C13/0007G11C13/0011G11C2013/0083G11C2013/0092G11C2213/71G11C2213/77G11C2213/78G11C2213/79
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Quick Facts
Patent No.
US 9,472,758
App. No.
14/538,763
Granted
Oct 18, 2016
Kind
B2
Abstract

The manufacturing of the non-volatile storage system includes depositing one or more layers of reversible resistance-switching material for a non-volatile storage element. Prior to operation, either during manufacturing or afterwards, a forming operation is performed. In one embodiment, the forming operation includes applying a forming voltage to the one or more layers of reversible resistance-switching material to form a first region that includes a resistor and a second region that can reversibly change resistance at a low current, the resistor is formed in response to the forming condition and is not deposited on the device. In some embodiments, programming the non-volatile storage element includes applying a programming voltage that increases in voltage over time at low current but does not exceed the final forming voltage.

Claims (57)

1. A method for use with non-volatile storage, comprising:

depositing one or more layers of reversible resistance-switching material for a non-volatile storage element;

applying a forming voltage to the one or more layers of reversible resistance-switching material to form a first region that includes a resistor and a second region that can reversibly change resistance, the second region is in series with the first region, the resistor is formed in response to applying the forming voltage; and

programming the non-volatile storage element;

the applying the forming voltage includes applying a voltage signal that increases in voltage over time and has a final forming voltage;

the non-volatile storage element is part of a monolithic three dimensional memory array of non-volatile storage elements that includes a plurality of global array lines, a plurality of vertically oriented local array lines connected to the monolithic three dimensional memory array of non-volatile storage elements, and a plurality of vertically oriented select devices that are above a substrate and are connected to the vertically oriented local array lines and the global array lines;

the programming includes applying a gate voltage signal to the vertically oriented select devices that is limited to be less than a maximum gate voltage;

the programming includes applying a programming voltage signal to the global array lines that is limited in magnitude to be less than the final forming voltage.

2. The method of claim 1 , wherein:

the applying the forming voltage is part of a forming process with a limiting current value.

3. The method of claim 2 , wherein the limiting current value is less than or equal to about 10 uA.

4. The method of claim 2 , wherein the limiting current value is less than or equal to about 3 uA.

5. The method of claim 2 , further comprising:

tuning a resistance of the resistor by adjusting the limiting current value.

6. The method of claim 1 , wherein:

the first region and the second region are formed in a single layer of reversible resistance-switching material in response to the forming voltage.

7. The method of claim 1 , wherein:

the one or more layers of reversible resistance-switching material comprises multiple layers of reversible resistance-switching material, the resistor is created in one of the layers of reversible resistance-switching material without depositing the resistor.

8. The method of claim 1 , further comprising:

tuning a resistance of the resistor by adjusting the forming voltage.

9. The method of claim 1 , wherein:

the applying a forming voltage includes applying a voltage pulse having a duration; and

the method further comprising tuning a resistance of the resistor by adjusting the pulse duration.

10. The method of claim 1 , wherein:

the applying the forming voltage creates a filament in the second region, the filament is separate from the resistor.

11. The method of claim 1 , wherein:

the non-volatile storage element is part of a monolithic three dimensional memory array of non-volatile storage elements.

12. A method for use with non-volatile storage, comprising:

depositing one or more layers of reversible resistance-switching material for a non-volatile storage element, the depositing the one or more layers of reversible resistance-switching material comprises:

depositing a particular layer of reversible resistance-switching material,

depositing a polysilicon layer adjacent the particular layer of reversible resistance-switching material, and

generating an interface layer between the polysilicon layer and the particular layer of reversible resistance-switching material by applying a thermal treatment; and

applying a forming voltage to the one or more layers of reversible resistance-switching material to form a first region that includes a resistor and a second region that can reversibly change resistance, the second region is in series with the first region, the resistor is formed in response to applying the forming voltage, the resistor is created in the interface layer in response to the forming voltage.

13. A method for use with non-volatile storage, comprising:

depositing one or more layers of reversible resistance-switching material for a non-volatile storage element, the depositing the one or more layers of reversible resistance-switching material comprises:

depositing a particular layer of reversible resistance-switching material,

depositing a polysilicon layer adjacent the particular layer of reversible resistance-switching material, and

generating an interface layer between the polysilicon layer and the particular layer of reversible resistance-switching material by applying a thermal treatment; and

applying a forming voltage to the reversible resistance-switching material to create a resistor and a filament separate from the resistor in the reversible resistance-switching material in response to the forming voltage, the resistor is created in the interface layer in response to the forming voltage.

14. The method of claim 13 , wherein:

the applying the forming voltage includes applying a voltage signal that increases in voltage over time and has a final forming voltage; and

the method further comprises programming the non-volatile storage element by applying a programming voltage that does not exceed the final forming voltage.

15. The method of claim 13 , wherein:

the resistor and a reversible resistance-switching region are formed in a single layer of reversible resistance-switching material in response to the forming voltage.

16. The method of claim 13 , wherein:

the non-volatile storage element is part of a monolithic three dimensional memory array of non-volatile storage elements.

17. A method for use with non-volatile storage, comprising:

applying a forming voltage to the one or more layers of reversible resistance-switching material to form a first region that includes a resistor and a second region that can reversibly change resistance, the second region is in series with the first region, the resistor is formed in response to applying the forming voltage;

the applying the forming voltage includes applying a voltage signal that increases in voltage over time and has a final forming voltage;

the one or more layers of reversible resistance-switching material are part of a non-volatile storage element;

the non-volatile storage element is part of a monolithic three dimensional memory of non-volatile storage elements that includes a plurality of global array lines, a plurality of vertically oriented local array lines connected to the monolithic three dimensional memory array of non-volatile storage elements, and a plurality of vertically oriented select devices that are above a substrate and are connected to the vertically oriented local array lines and the global array lines;

the method further comprises programming the non-volatile storage element by applying a programming voltage that does not exceed the final forming voltage;

the programming includes applying a gate voltage signal to the vertically oriented select devices is limited to be less than a maximum gate voltage; and

the programming includes applying a programming voltage signal to the global array lines that is limited in magnitude to be less than the final forming voltage.

18. A method for use with non-volatile storage, comprising:

depositing one or more layers of reversible resistance-switching material including depositing a particular layer of reversible resistance-switching material, depositing a polysilicon layer adjacent the particular layer of reversible resistance-switching material and generating an interface layer in between the polysilicon layer and the particular layer of reversible resistance-switching material by applying a thermal treatment; and

applying a forming voltage to the one or more layers of reversible resistance-switching material to form a first region that includes a resistor and a second region that can reversibly change resistance, the second region is in series with the first region, the resistor is formed in response to applying the forming voltage, the resistor is created in the interface layer in response to the forming voltage.

Assignments (4)
CHANGE OF NAME Recorded May 25, 2016
From: SANDISK TECHNOLOGIES INC
To: SANDISK TECHNOLOGIES LLC
Reel/Frame 038807/0807 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT LISTED PATENT NUMBER 8853569 TO THE CORRECT PATENT NUMBER 8883569 PREVIOUSLY RECORDED ON REEL 038300 FRAME 0665. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Apr 25, 2016
From: SANDISK 3D LLC
To: SANDISK TECHNOLOGIES INC.
Reel/Frame 038520/0552 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 30, 2016
From: SANDISK 3D LLC.
To: SANDISK TECHNOLOGIES INC.
Reel/Frame 038300/0665 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 12, 2014
From: LAN, ZHIDA; BANDYOPADHYAY, ABHIJIT; PETTI, CHRISTOPHER; XIAO, LI; NAGAVARAPU, GIRISH
To: SANDISK 3D LLC
Reel/Frame 034151/0872 →
Continuity (1)
Related Publication 20160133836A1 · May 12, 2016