Sense amplifier including a single-transistor amplifier and level shifter and methods therefor
View Patent ↗Methods are provided for use with a memory array that includes a selected memory cell coupled to a selected word line and a selected bit line, with the selected word line biased at a read voltage. The method include coupling a sense amplifier to the selected bit line, the sense amplifier including a capacitor integrator, a single-transistor amplifier and a level shifter, maintaining the selected bit line at a voltage of substantially 0V using the single-transistor amplifier and the level shifter, and integrating a selected bit line current on the capacitor integrator.
1. A method for use with a memory array comprising a selected memory cell coupled to a selected word line and a selected bit line, the selected word line biased at a read voltage, the method comprising:
coupling a sense amplifier to the selected bit line, the sense amplifier comprising a capacitor integrator, a single-transistor amplifier and a level shifter, wherein the capacitor integrator has a first terminal coupled to the single-transistor amplifier, and a second terminal coupled to a control terminal of the level shifter;
maintaining the selected bit line at a voltage of substantially 0V using the single-transistor amplifier and the level shifter;
integrating a selected bit line current on the capacitor integrator; and
performing a read of the selected memory cell using the integrated selected bit line current.
2. The method of claim 1 , wherein the read voltage is greater than 0V.
3. The method of claim 1 , wherein:
the single-transistor amplifier comprises a first transistor that comprises an n-MOS transistor comprising a threshold voltage;
the level shifter comprises a second transistor that comprises a p-MOS transistor comprising a threshold voltage; and
a magnitude of the threshold voltage of the first transistor is less than or substantially equal to a magnitude of the threshold voltage of the second transistor.
4. The method of claim 1 , further comprising comparing the integrated bit line current to a reference voltage.
5. The method of claim 1 , further comprising:
coupling an output of the capacitor integrator to a third transistor;
turning ON the third transistor if the selected bit line current has a first predetermined value; and
turning OFF the third transistor if the selected bit line current has a second predetermined value.
6. A sense amplifier for use with a memory array comprising a selected memory cell coupled to a selected word line and a selected bit line, the selected word line biased at a read voltage, the sense amplifier comprising:
an input terminal coupled to the selected bit line and coupled to a first terminal of a capacitor;
a first transistor comprising a first terminal coupled to a second terminal of the capacitor, a second terminal and a third terminal coupled to a GROUND terminal;
a second transistor comprising a first terminal coupled to the second terminal of the first transistor, a second terminal coupled to the first terminal of the capacitor, and a third terminal coupled to the GROUND terminal;
a first current source coupled between a positive supply terminal and the second terminal of the capacitor;
a second current source coupled between the positive supply terminal and the first terminal of the second transistor;
a third transistor comprising a first terminal coupled to an output terminal of the sense amplifier, a second terminal coupled to the second terminal of the capacitor, and a third terminal coupled to the GROUND terminal; and
a load circuit coupled between the positive supply terminal and the first terminal of the third transistor.
7. The sense amplifier of claim 6 , wherein the read voltage is greater than 0V.
8. The sense amplifier of claim 6 , wherein the sense amplifier is configured to maintain the selected bit line at a voltage of substantially 0V.
9. The sense amplifier of claim 6 , wherein the first transistor and the second transistor and capacitor are configured to maintain the selected bit line at a voltage of substantially 0V.
10. The sense amplifier of claim 6 , wherein:
the first transistor comprises an n-MOS transistor comprising a threshold voltage;
the second transistor comprises a p-MOS transistor comprising a threshold voltage; and
a magnitude of the threshold voltage of the first transistor is less than or substantially equal to a magnitude of the threshold voltage of the second transistor.
11. The sense amplifier of claim 6 , wherein the third transistor comprises an n-MOS transistor.
12. The sense amplifier of claim 6 , wherein the capacitor comprises a capacitance value between about 10 fF and about 100 fF.
13. The sense amplifier of claim 6 , wherein the load circuit comprises a diode-connected p-MOS transistor.
14. The sense amplifier of claim 6 , wherein the first current source is configured to selectively charge the capacitor to an initial voltage.
15. The sense amplifier of claim 6 , wherein the second current source is configured to bias the second transistor in saturation.
16. A method for use with a memory array comprising a selected memory cell coupled to a selected word line and a selected bit line, the selected word line biased at a read voltage, the method comprising:
coupling the selected bit line to a first terminal of a capacitor;
coupling a first terminal of a first transistor to a second terminal of the capacitor;
coupling a third terminal of the first transistor to a GROUND terminal;
coupling a first terminal of a second transistor to a second terminal of the first transistor;
coupling a second terminal of the second transistor to the first terminal of the capacitor;
coupling a third terminal of the second transistor to the GROUND terminal;
coupling a first current source between a positive supply terminal and the second terminal of the capacitor;
coupling a second current source between the positive supply terminal and the first terminal of the second transistor;
coupling a first terminal of a third transistor comprising to an output terminal of the sense amplifier;
coupling, a second terminal of the third transistor to the second terminal of the capacitor;
coupling a third terminal of the third transistor to the GROUND terminal; and
coupling a load circuit coupled between the positive supply terminal and the first terminal of the third transistor.
17. The method of claim 16 , wherein the read voltage is greater than 0V.
18. The method of claim 16 , further comprising using the first transistor and the second transistor to maintain the selected bit line at a voltage of about 0V.
19. The method of claim 16 , wherein:
the first transistor comprises an n-MOS transistor comprising a threshold voltage;
the second transistor comprises a p-MOS transistor comprising a threshold voltage; and
a magnitude of the threshold voltage of the first transistor is less than or substantially equal to a magnitude of the threshold voltage of the second transistor.
20. The method of claim 16 , wherein the third transistor comprises an n-MOS transistor.