IP Library Granted Patent US 9,480,193
Granted Patent B2
US 9,480,193 · App. 14/542,778 · Granted Oct 25, 2016

Load detection circuit and method

Inventors: Sam Vermeir (Hofstade, BE); Leo Aichriedler (Ebersberg, DE)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H05K13/00H05B33/0887G01R31/026G01R31/2621Y10T29/49117Y10T29/49169
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,480,193
App. No.
14/542,778
Granted
Oct 25, 2016
Kind
B2
Abstract

In one embodiment, a load detection circuit may include a first circuit configured to control a first transistor to form a load current to a load in a first operating mode of the load detection circuit, a second circuit configured to be coupled to form at least a portion of the load current in a second operating mode of the load detection circuit, and a detection circuit configured to detect the control electrode of the first transistor having a value that is less than a threshold value of the first transistor.

Claims (32)

1. A load detection circuit comprising:

a driver circuit configured to form a drive signal to drive a control electrode of a drive transistor with a first control signal to form a voltage between a first current carrying electrode of the drive transistor and a second current carrying electrode of the drive transistor;

a first switch coupled to selectively couple a first signal to the driver circuit responsively to a first state of a mode signal and to selective couple a second signal to the driver circuit responsively to a second state of the mode signal wherein the driver circuit is configured to form the voltage to have a first value responsively to receiving the first signal and to form the voltage to have a second value responsively to receiving the second signal;

a diagnostic transistor configured to be coupled in parallel with the drive transistor, the diagnostic transistor having a control electrode configured to receive a second control signal, the second control signal having a third value responsively to the first state of the mode signal and having a fourth value responsively to the second state of the mode signal, wherein the third value substantially disables the diagnostic transistor; and

a comparator configured to detect the control electrode of the drive transistor having a fifth value that is less than a threshold voltage of the drive transistor in response to the second state of the mode signal.

2. The load detection circuit of claim 1 wherein the driver circuit is configured to form the drive signal to enable the drive transistor in response to receiving the first signal and in response to receiving the second signal.

3. The load detection circuit of claim 1 wherein the drive transistor and the driver circuit form a closed control loop for the second state of the mode signal.

4. The load detection circuit of claim 1 wherein the comparator has a first input coupled to receive the first control signal and a second input coupled to receive a reference signal, the reference signal having a sixth value that is representative of no greater than the threshold voltage of the drive transistor.

5. The load detection circuit of claim 1 wherein the driver circuit has a first input coupled to receive a signal on the first current carrying electrode of the drive transistor, a second input coupled to the first switch to receive the first and second signals, and an output coupled to the control electrode of the drive transistor.

6. The load detection circuit of claim 1 wherein the diagnostic transistor has the control electrode coupled to receive the second control signal from a second switch, the second switch configured to couple the control electrode of the diagnostic transistor to a first current carrying electrode of the diagnostic transistor responsively to the first state of the mode signal and to couple the control electrode of the diagnostic transistor to receive the fourth value from a reference circuit responsively to the second state of the mode signal.

7. The load detection circuit of claim 1 further including a control circuit configured to form the first and second state of the mode signal wherein the first state of the mode signal has a longer time interval than the second state of the mode signal.

8. The load detection circuit of claim 1 wherein the drive transistor is an N-channel MOS transistor and the diagnostic transistor is one of an N-channel transistor or a P-channel MOS transistor.

9. The load detection circuit of claim 1 wherein a first current carrying electrode of the diagnostic transistor is configured for coupling to the first current carrying electrode of the drive transistor, a second current carrying electrode of the diagnostic transistor is configured for coupling to the second current carrying electrode of the drive transistor, and the control electrode of the diagnostic transistor is not coupled to the control electrode of the drive transistor.

10. A method of forming a load detection circuit comprising:

providing a current source;

configuring the load detection circuit to operate in a first mode and selectively disable the current source and selectively apply a first control signal having a first value to a first transistor to control the first transistor to form a load current to a load;

configuring the load detection circuit to operate in a second mode and selectively enable the current source to form at least a portion of the load current to the load and to selectively apply a second control signal having a second value to the first transistor to control the first transistor and form a first voltage across the first transistor wherein the first voltage is no less than the second value; and

configuring a detect circuit to detect the second control signal having the second value that is substantially less than a threshold voltage of the first transistor.

11. The method of claim 10 wherein configuring the detect circuit to detect the second control signal includes configuring the detect circuit to operate in the second mode to detect the second control signal having the second value that is substantially less than the threshold voltage.

12. The method of claim 10 wherein configuring the current source for coupling in parallel to the first transistor includes coupling a first current carrying electrode of a second transistor to a terminal that is configured for coupling to a first current carrying electrode of the first transistor, and coupling a second current carrying electrode of the second transistor to a terminal that is configured for coupling to a second current carrying electrode of the first transistor.

13. The method of claim 10 wherein configuring the load detection circuit to operate in the second mode includes configuring the first transistor and a driver circuit to operate in a closed loop configuration to control the first transistor and form the first voltage across the first transistor.

14. The method of claim 10 wherein configuring the load detection circuit to operate in the second mode includes configuring the load detection circuit to control the first transistor to form another portion of the load current.

15. The method of claim 10 wherein configuring the load detection circuit to operate in the second mode includes configuring the load detection circuit to selectively apply the second control signal to the first transistor wherein the second control signal has substantially the first value.

16. A load detection circuit comprising:

a first circuit configured to control a first transistor to form a load current to a load in a first operating mode of the load detection circuit;

a second circuit configured to selectively form a portion of the load current in response to a second operating mode of the load detection circuit but not in the first operating mode;

the first circuit configured to control the first transistor in a closed loop configuration to form a voltage drop across the first transistor in the second operating mode; and

a detection circuit configured to detect the load current is less than a threshold value of the load current.

17. The load detection circuit of claim 16 wherein the first circuit includes an amplifier configured to selectively apply a first signal having a first value to a control electrode of the first transistor in response to the first operating mode, and to apply a second signal having a second value to the control electrode of the first transistor in response to the second operating mode.

18. The load detection circuit of claim 17 wherein the first value is less than the second value.

19. The load detection circuit of claim 16 wherein the second circuit includes a selectable current source having a second transistor and a third circuit configured to control the second transistor to supply the portion of the load current wherein the third circuit is configured to couple a control electrode of the second transistor to a first control signal having a first value that is less than a threshold value of the second transistor in response to the first operating mode, and to couple the control electrode of the second transistor to a second control signal having a second value that is greater than the threshold value of the second transistor.

20. The load detection circuit of claim 16 wherein the detection circuit includes a comparator having a first input coupled to a control electrode of the first transistor and a second input coupled to receive a reference signal having a reference value that is less than the threshold value of the first transistor.

Assignments (4)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 30, 2015
From: VERMEIR, SAM; AICHRIEDLER, LEO
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 034852/0838 →
Continuity (2)
Provisional Application 61908123 · Nov 24, 2013
Related Publication 20150145562A1 · May 28, 2015