IP Library Granted Patent US 9,986,646
Granted Patent B2
US 9,986,646 · App. 14/549,934 · Granted May 29, 2018

Packaged electronic devices with top terminations, and methods of manufacture thereof

Inventors: Lakshminarayan Viswanathan (Phoenix, AZ); Audel A. Sanchez (Tempe, AZ); Fernando A. Santos (Chandler, AZ); Jerry L. White (Glendale, AZ)
Assignee: NXP USA, INC.
H05K3/284H01L21/56H01L23/22H01L23/28H01L31/0203H01L31/048H01L33/52H05K1/185H05K3/3421H05K9/0052H05K9/0081H05K2201/10166H05K2201/10371H05K2201/10977H05K2203/1316H05K2203/1327
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Quick Facts
Patent No.
US 9,986,646
App. No.
14/549,934
Granted
May 29, 2018
Kind
B2
Abstract

An embodiment of an electronic device includes a circuit component (e.g., a transistor or other component) coupled to the top surface of a substrate. Encapsulation is formed over the substrate and the component. An opening in the encapsulation extends from the encapsulation top surface to a conductive feature on the top surface of the component. A conductive termination structure within the encapsulation opening extends from the conductive feature to the encapsulation top surface. The device also may include a second circuit physically coupled to the encapsulation top surface and electrically coupled to the component through the conductive termination structure. In an alternate embodiment, the conductive termination structure may be located in a trench in the encapsulation that extends between two circuits that are embedded within the encapsulation, where the conductive termination structure is configured to reduce electromagnetic coupling between the two circuits during device operation.

Claims (22)

1. A device comprising:

a substrate having a substrate top surface;

a transistor of an amplifier circuit, the transistor coupled to the substrate top surface and having a transistor top surface, wherein the transistor includes a first die pad exposed at the transistor top surface;

an encapsulation having an encapsulation top surface over at least a portion of the substrate top surface and the transistor top surface, wherein the encapsulation includes an opening extending from the encapsulation top surface to the first die pad of the transistor;

a first conductive termination structure within the opening in the encapsulation, wherein the first conductive termination structure is a solid conductive structure that is directly physically coupled to the first die pad, the first conductive termination structure extends from the first die pad to the encapsulation top surface, and an entirety of the first conductive structure from the first die pad to the encapsulation top surface is formed from a bulk conductive material; and

a second circuit that forms a portion of the amplifier circuit, wherein the second circuit is physically coupled to the encapsulation top surface and electrically coupled to the transistor through the first conductive termination structure.

2. The device of claim 1 , wherein the device further comprises

a second conductive termination structure extending from a second die pad of the transistor to the encapsulation top surface.

3. The device of claim 1 , wherein the second circuit includes one or more components of an input impedance matching circuit.

4. The device of claim 1 , wherein the second circuit includes one or more components of an output impedance matching circuit.

5. The device of claim 1 , wherein the top substrate surface is conductive, and the device further comprising a second conductive termination structure that extends from the substrate top surface to the encapsulation top surface.

6. The device of claim 1 , wherein the bulk conductive material is selected from a thick film conductive paste, a conductive polymer, and a sintered paste.

7. A device comprising:

a substrate having a substrate top surface;

a transistor of an amplifier circuit, the transistor coupled to the substrate top surface and having a transistor top surface, wherein the transistor includes a first die pad exposed at the transistor top surface;

an encapsulation having an encapsulation top surface over at least a portion of the substrate top surface and the transistor top surface, wherein the encapsulation includes an opening extending from the encapsulation top surface to the first die pad of the transistor;

a first conductive termination structure within the opening in the encapsulation, wherein the first conductive termination structure is a solid conductive structure that is directly physically coupled to the first die pad, the first conductive termination structure extends from the first die pad to the encapsulation top surface, and an entirety of the first conductive structure from the first die pad to the encapsulation top surface includes plated metal in direct contact with the first die pad, and a conductive bulk over the plated metal; and

a second circuit that forms a portion of the amplifier circuit, wherein the second circuit is physically coupled to the encapsulation top surface and electrically coupled to the transistor through the first conductive termination structure.

8. The device of claim 7 , wherein the device further comprises

a second conductive termination structure extending from a second die pad of the transistor to the encapsulation top surface.

9. The device of claim 7 , wherein the second circuit includes one or more components of an input impedance matching circuit.

10. The device of claim 7 , wherein the second circuit includes one or more components of an output impedance matching circuit.

Assignments (11)
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040626 FRAME: 0683. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME EFFECTIVE NOVEMBER 7, 2016. Recorded Jan 12, 2017
From: NXP SEMICONDUCTORS USA, INC. (MERGED INTO); FREESCALE SEMICONDUCTOR, INC. (UNDER)
To: NXP USA, INC.
Reel/Frame 041414/0883 →
CHANGE OF NAME Recorded Nov 16, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040626/0683 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037444/0444 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037444/0535 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037358/0001 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Feb 18, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 035033/0001 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Feb 18, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 035034/0019 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Feb 18, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 035033/0923 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 21, 2014
From: VISWANATHAN, LAKSHMINARAYAN; SANCHEZ, AUDEL A.; SANTOS, FERNANDO A.; WHITE, JERRY L.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 034229/0811 →
Continuity (1)
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