IP Library Granted Patent US 9,589,928
Granted Patent B2
US 9,589,928 · App. 14/552,497 · Granted Mar 7, 2017

Combined QFN and QFP semiconductor package

Inventors: Zhigang Bai (Tianjin, CN); Jinzhong Yao (Tianjin, CN); Lan Chu Tan (Singapore, SG)
Assignee: NXP USA, INC.
H01L24/85H01L23/49537H01L23/49541H01L23/49548H01L23/49551H01L23/49861H01L21/565H01L23/3121H01L24/29H01L24/32H01L24/45H01L24/48H01L24/49H01L24/73H01L2224/05599H01L2224/2919H01L2224/29339H01L2224/32245H01L2224/456H01L2224/4569H01L2224/45144H01L2224/45147H01L2224/45565H01L2224/48091H01L2224/48247H01L2224/49109H01L2224/73265H01L2224/85399H01L2224/92247H01L2924/00014H01L2924/14H01L2924/1433H01L2924/1434H01L2924/181
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Quick Facts
Patent No.
US 9,589,928
App. No.
14/552,497
Granted
Mar 7, 2017
Kind
B2
Abstract

A semiconductor package includes a first lead frame type having a first type of package leads and a pre-molded portion, and a second lead frame type having a second type of package leads that surround a die pad and are supported by the pre-molded portion. An integrated circuit is attached to the die pad and electrically connected to the first and second types of leads with bond wires. A mold compound, which forms a mold cap, covers the first and second lead frame types, the integrated circuit and the bond wires. The first lead frame type may be a QFP type and the second lead frame type may be a QFN type.

Claims (37)

1. A semiconductor package, comprising:

a die pad having an upper surface and a lower surface;

an integrated circuit attached on the upper surface of the die pad;

a plurality of first package type leads surrounding the die pad, wherein each of the plurality of first package type leads is electrically connected to the integrated circuit with first bond wires;

a plurality of second package type leads that surround the first package type leads, wherein the second package type leads have proximal ends that are positioned above the plurality of first package type leads, wherein the proximal ends of the second package type leads are electrically connected to the integrated circuit with second bond wires, and wherein the second package type leads are of a different lead type than the first package type leads; and

a mold cap that at least partially covers the die pad, the integrated circuit, the plurality of first and second package type leads, and the first and second bond wires;

a pre-molded portion for positioning the first package type leads and supporting the second package type leads over the first package type leads, wherein the pre-molded portion includes a structure located between leads of the plurality of first package type leads and leads of the plurality of second package type leads in a direction orthogonal to the upper surface of the die pad, wherein the structure is formed separately from the mold cap.

2. The semiconductor package of claim 1 , wherein the second package type leads have intermediate portions that project from sides of the mold cap and distal ends that lie in a parallel plane with the first package type leads.

3. The semiconductor package of claim 2 , wherein a lower surface of the die pad not covered by the mold cap is exposed.

4. The semiconductor package of claim 2 , wherein a lower surface of the die pad is covered by the mold cap.

5. The semiconductor package of claim 1 , wherein the plurality of the first package type leads are of a lead type for a quad flat non-leaded package (QFN) and the plurality of the second package type leads are of a lead type for a quad flat package (QFP).

6. The semiconductor package of claim 1 , further comprising a ground ring surrounded by the first package type leads and electrically coupled to the integrated circuit.

7. The semiconductor package of claim 1 , further comprising a power ring surrounded by the first package type leads and electrically coupled to the integrated circuit.

8. The semiconductor package of claim 1 , wherein the second package type leads are attached to the pre-molded portion with adhesive.

9. The semiconductor package of claim 1 , further comprising an adhesive attaching leads of the plurality of second package type leads to the structure of the pre-molded portion.

10. The semiconductor package of claim 1 , wherein the structure includes a plastic material.

11. The semiconductor package of claim 1 , wherein the structure includes an encapsulant material.

12. The semiconductor package of claim 1 , wherein the structure includes tape.

13. The semiconductor package of claim 1 wherein at least a portion of each lead of the plurality of first package type leads is encapsulated in the pre-molded portion.

14. The semiconductor package of claim 1 wherein a lower portion of the pre-molded portion not covered by the mold cap is exposed.

15. The semiconductor package of claim 1 wherein the pre-molded portion includes an opening, wherein the die pad is located in an area of the opening.

16. A semiconductor package, comprising:

a die pad having an upper surface and a lower surface;

an integrated circuit attached on the upper surface of the die pad;

a pre-molded assembly comprising a plurality of first package type leads and mold material, wherein at least a portion of each lead of the plurality of first package type leads is encapsulated in the mold material, wherein each of the plurality of first package type leads is electrically connected to the integrated circuit with first bond wires;

a plurality of second package type leads, wherein the second package type leads have proximal ends that are positioned above the plurality of first package type leads, wherein the proximal ends of the second package type leads are electrically connected to the integrated circuit with second bond wires, and wherein the second package type leads are of a different lead type than the first package type leads; and

a mold cap that at least partially covers the die pad, the integrated circuit, the plurality of second package type leads, the pre-molded assembly, and the first and second bond wires, wherein the mold cap and the mold material are separately formed;

wherein mold material of the pre-molded assembly is located between leads of the plurality of first package type leads and leads of the plurality of second package type leads in a direction orthogonal to the upper surface of the die pad.

17. The semiconductor package of claim 16 , wherein the second package type leads are attached to the pre-molded assembly with adhesive.

18. The semiconductor package of claim 16 wherein the pre-molded assembly includes an opening, wherein the die pad is located in an area of the opening.

19. A semiconductor package, comprising:

a die pad having an upper surface and a lower surface;

an integrated circuit attached on the upper surface of the die pad;

a pre-molded assembly comprising a plurality of first package type leads surrounding the die pad, wherein each of the plurality of first package type leads is electrically connected to the integrated circuit with first bond wires;

a plurality of second package type leads that surround the first package type leads, wherein the second package type leads have proximal ends that are positioned above the plurality of first package type leads, wherein the proximal ends of the second package type leads are electrically connected to the integrated circuit with second bond wires, and wherein the second package type leads are of a different lead type than the first package type leads; and

a mold cap that at least partially covers the die pad, the integrated circuit, the plurality of second package type leads, the pre-molded assembly, and the first and second bond wires;

wherein a structure of the pre-molded assembly is located between leads of the plurality of first package type leads and leads of the plurality of second package type leads in a direction orthogonal to the upper surface of the die pad, wherein the structure is of a material different than a material of the mold cap.

Assignments (11)
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040626 FRAME: 0683. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME EFFECTIVE NOVEMBER 7, 2016. Recorded Jan 12, 2017
From: NXP SEMICONDUCTORS USA, INC. (MERGED INTO); FREESCALE SEMICONDUCTOR, INC. (UNDER)
To: NXP USA, INC.
Reel/Frame 041414/0883 →
CHANGE OF NAME Recorded Nov 16, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040626/0683 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037444/0444 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037444/0535 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037358/0001 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Feb 18, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 035033/0001 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Feb 18, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 035034/0019 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Feb 18, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 035033/0923 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 25, 2014
From: BAI, ZHIGANG; YAO, JINZHONG; TAN, LAN CHU
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 034255/0279 →
Priority Claims (1)
CN 2014 1 0199269 · Apr 15, 2014 · national
Continuity (1)
Related Publication 20150294924A1 · Oct 15, 2015