Protective packaging for integrated circuit device
A method for packaging an integrated circuit (IC) device in which conventional manufacturing steps of mechanically bonding a die to a corresponding interconnecting substrate, wire bonding the die, and encapsulating the die in a protective shell are replaced by a single manufacturing step that includes thermally treating an appropriate assembly of parts to both form proper electrical connections for the die in the resulting IC package and cause the molding compound(s) to encapsulate the die in a protective enclosure.
1. A packaged integrated circuit (IC) device, comprising:
a first package substrate;
a second package substrate;
a die attached at a first side thereof to the first package substrate and further attached at an opposite second side thereof to the second package substrate, wherein the die is positioned within an enclosure defined by the first package substrate and the second package substrate; and
a body of a molding compound encapsulating the die and attaching the die to the first and second package substrates inside the enclosure, wherein the body comprises:
a first layer that attaches the first side of the die to the first package substrate, said first layer comprising a first molding compound; and
a second layer that attaches the second side of the die to the second package substrate, said second layer comprising a second molding compound different from the first molding compound.
2. The packaged IC device of claim 1 , wherein the body fills up gaps between the die and the first and second package substrates inside the enclosure.
3. The packaged IC device of claim 1 , wherein the body comprises a layer of the molding compound that directly attaches the first and second package substrates to one another outside a footprint of the die.
4. The packaged IC device of claim 1 , wherein the second package substrate comprises a plurality of electrically conducting vias, each configured to electrically connect the die to a respective solder bump attached to an outer surface of the second package substrate.
5. The packaged IC device of claim 1 , further comprising a plurality of solder bumps connected to the substrate for electrically connecting the packaged IC device on a circuit board.