High-gain low-noise preamplifier and associated amplification and common-mode control method
View Patent ↗A preamplifier includes a differential pair of transistors receiving a bias current having a differential input and a differential output, a first resistor coupled to a first differential output node, a first transistor having a current path coupled between the first resistor and a power supply, a second resistor coupled to the first differential output node, a second transistor having a current path coupled between the second resistor and the power supply, a third resistor coupled to a second differential output node, a third transistor having a current path coupled between the third resistor and the power supply, a fourth resistor coupled to the second differential output node, and a fourth transistor having a current path coupled between the fourth resistor and the power supply, wherein a source of the second and third transistors are coupled together.
1. A preamplifier comprising:
a differential pair of transistors having a differential input and a differential output; and
a plurality of load circuits coupled between the differential output and a source of supply voltage, wherein each load circuit comprises a transistor and a resistor in series combination, wherein sources of two transistors in two load circuits are directly coupled together, and wherein a drain of at least one of the transistors in the load circuits is coupled directly to the source of supply voltage,
wherein a gate of the transistors in the load circuits receive a common-mode signal, the common-mode signal is provided by a switched capacitor circuit, and the switched capacitor circuit is part of a loop regulating the common-mode of the outputs of the preamplifier itself.
2. The preamplifier of claim 1 wherein the switched capacitor circuit is part of a loop regulating the common-mode of the outputs of an operational amplifier comprising the preamplifier, and at least one additional stage coupled to the differential output of the preamplifier.
3. The preamplifier of claim 1 wherein the switched capacitor circuit is part of a loop regulating the common-mode of the outputs of one of the additional stages of an operational amplifier comprising the preamplifier, and at least one additional stage coupled to the differential output of the preamplifier.
4. The preamplifier of claim 1 wherein the differential pair of transistors receives a bias current.
5. The preamplifier of claim 1 wherein the differential pair of transistors comprises an N-channel Field Effect Transistor (FET), a P-channel FET, an NPN Bipolar Junction Transistor (BJT), or a PNP BJT.
6. The preamplifier of claim 1 wherein the transistors in the load circuits each comprise an N-channel FET, a P-channel FET, an NPN BJT, or a PNP BJT.
7. The preamplifier of claim 1 wherein the resistors in the load circuits each comprise a polysilicon, p- or n-diffusion, metal, SiCr, or NiCr resistor.
8. A preamplifier comprising:
a differential pair of transistors having a differential input and a differential output; and
a plurality of load circuits coupled between the differential output and a source of supply voltage, wherein each load circuit comprises a transistor and a resistor in series combination, wherein sources of two transistors in two load circuits are directly coupled together, and wherein a drain of at least one of the transistors in the load circuits is coupled directly to the source of supply voltage,
wherein a gate of the transistors in the load circuits receive a common-mode signal, the common-mode signal is provided by a continuous-time circuit, and the continuous-time circuit is part of a loop regulating the common-mode of the outputs of the preamplifier itself.
9. The preamplifier of claim 8 wherein the continuous-time circuit is part of a loop regulating the common-mode of the outputs of an operational amplifier comprising the preamplifier, and at least one additional stage coupled to the differential output of the preamplifier.
10. The preamplifier of claim 8 wherein the continuous-time circuit is part of a loop regulating the common-mode of the outputs of one of the additional stages of an operational amplifier comprising the preamplifier, and at least one additional stage coupled to the differential output of the preamplifier.
11. The preamplifier of claim 8 wherein the differential pair of transistors receives a bias current.
12. The preamplifier of claim 8 wherein the differential pair of transistors comprises an N-channel Field Effect Transistor (FET), a P-channel FET, an NPN Bipolar Junction Transistor (BJT), or a PNP BJT.
13. The preamplifier of claim 8 wherein the transistors in the load circuits each comprise an N-channel FET, a P-channel FET, an NPN BJT, or a PNP BJT.
14. The preamplifier of claim 8 wherein the resistors in the load circuits each comprise a polysilicon, p- or n-diffusion, metal, SiCr, or NiCr resistor.