FinFET body contact and method of making same
A semiconductor device may include body contacts on a finFET device for ESD protection. The semiconductor device comprises a semiconductor fin, a source/drain region and a body contact. The source/drain region and the body contact are in the semiconductor fin. A portion of the fin is laterally between the source/drain region and the body contact. The semiconductor fin is on a substrate.
1. A semiconductor device comprising:
a fin extending from a substrate;
a first gate and a second gate over the fin;
a first source/drain region in the fin, the first source/drain region being between the first gate and the second gate;
a first body contact in the fin, the second gate partially overlapping the first body contact; and
a third gate over the fin between the first source/drain region and the first body contact.
2. The semiconductor device of claim 1 , wherein the third gate is directly over a first portion of the fin, the first portion being a semiconductor material.
3. The semiconductor device of claim 1 , wherein the fin contains dopants of a first conductivity type, the first source/drain region contains dopants of a second conductivity type, and the first body contact contains dopants of the first conductivity type.
4. The semiconductor device of claim 3 , wherein the first conductivity type is p-type and the second conductivity type is n-type.
5. The semiconductor device of claim 1 further comprising:
a first isolation region in the fin, the second gate partially overlapping the first isolation region.
6. The semiconductor device of claim 1 further comprising:
a fourth gate over the fin;
a second source/drain region between the first gate and the fourth gate; and
a second body contact in the fin, the fourth gate partially overlapping the second body contact.
7. The semiconductor device of claim 6 , wherein the first gate is an active gate, and wherein the second and fourth gates are dummy gates.
8. The semiconductor device of claim 1 , wherein the first gate is an active gate, and wherein the second and third gates are dummy gates.
9. A semiconductor device comprising:
a semiconductor fin raised above a substrate;
a first active gate over the semiconductor fin;
a first dummy gate over the semiconductor fin;
a first source/drain region in the semiconductor fin, the first source/drain region being between the first active gate and the first dummy gate, the first source/drain region being adjacent a first side of the first dummy gate;
a first body contact in the semiconductor fin, the first body contact being adjacent a second side of the first dummy gate, the second side being opposite the first side, the first dummy gate being aligned with the first body contact; and
a first spacer overlapping the first body contact.
10. The semiconductor device of claim 9 , wherein the first dummy gate is over a first portion of the semiconductor fin, the first portion extending from the first body contact to the first source/drain region, the first portion being a semiconductor material.
11. The semiconductor device of claim 9 further comprising:
a second dummy gate over the semiconductor fin;
a second source/drain region in the semiconductor fin, the second source/drain region being between the first active gate the second dummy gate; and
a second body contact in the semiconductor fin, the second body contact being adjacent the second dummy gate.
12. The semiconductor device of claim 11 , wherein the second dummy gate is over a second portion of the semiconductor fin, the second portion extending from the second body contact to the second source/drain region, the second portion being a semiconductor material.
13. The semiconductor device of claim 11 , wherein the second dummy gate is aligned with the second body contact.
14. The semiconductor device of claim 11 further comprising:
a second spacer overlapping the second body contact.
15. The semiconductor device of claim 9 further comprising:
a third dummy gate over the semiconductor fin, the first body contact being between the third dummy gate the first dummy gate; and
a first isolation region in the semiconductor fin, the third dummy gate partially overlapping the first isolation region.
16. The semiconductor device of claim 9 , wherein the semiconductor fin contains dopants of a first conductivity type, the first source/drain region contains dopants of a second conductivity type, and the first body contact contains dopants of the first conductivity type.
17. A device comprising:
a fin extending from a substrate;
a first gate structure on a top surface and sidewalls of the fin;
a second gate structure on the top surface and sidewalls of the fin;
a third gate structure on the top surface and sidewalls of the fin;
a first source/drain region in the fin, the first source/drain region being between the first gate structure and the second gate structure;
a second source/drain region in the fin, the second source/drain region being between the first gate structure and the third gate structure;
a first body contact in the fin, the second gate structure being between the first source/drain region and the first body contact; and
a second body contact in the fin, the third gate structure being between the second source/drain region and the second body contact.
18. The device of claim 17 further comprising:
a third source/drain region in the fin, the third source/drain region being laterally spaced from the second source/drain region in a direction opposite the first source/drain region.
19. The device of claim 17 further comprising:
a fourth gate structure on the top surface and sidewalls of the fin; and
an isolation region in the fin adjoining the first body contact, the fourth gate structure partially overlapping the isolation region and partially overlapping the first body contact.
20. The device of claim 17 , wherein the first gate structure is an active gate, and the second gate structure and the third gate structure are dummy gates.