Apparatus and method for processing trace data streams
An apparatus comprising: a lower-layer decoder configured to decode a data stream formatted according to a lower-layer protocol that interleaves portions of a first data stream and one or more additional data streams to produce separated data streams comprising the first data stream and separately the one or more additional data streams; and a higher-layer decoder configured to decode the first data stream formatted according to a higher-layer protocol to produce trace data, the higher-layer decoder comprising: synchronization logic configured to process the first data stream to detect a data pattern within the first data stream as a synchronization event; and decoding logic configured to use the synchronization event to synchronize decoding of the received first data stream to produce the trace data.
1. An apparatus comprising:
a lower-layer decoder configured to decode a data stream formatted according to a lower-layer protocol that interleaves portions of a first data stream and one or more additional data streams to produce separated data streams comprising the first data stream and separately the one or more additional data streams; and
a higher-layer decoder configured to decode a first data stream formatted according to a higher-layer protocol to produce trace data, the higher-layer decoder comprising:
synchronisation logic configured to process the first data stream to detect a data pattern within the first data stream as a synchronisation event; and
decoding logic configured to use the synchronisation event to synchronise decoding of the received first data stream to produce the trace data.
2. The apparatus as claimed in claim 1 , wherein the data pattern is a bit pattern spread over one or more distinct data sequences.
3. The apparatus as claimed in claim 2 , wherein the bit pattern is a reserved bit sequence.
4. The apparatus as claimed in claim 3 , wherein the reserved bit sequence is a unique message header.
5. The apparatus as claimed in claim 1 , wherein the data pattern is a pattern of time-separated data sequences corresponding to a pattern of time separated data sequences allowed according to the higher-layer protocol.
6. The apparatus as claimed in claim 5 , wherein the pattern of time-separated data sequences allowed according to the higher-layer protocol is an allowed pattern of message headers.
7. The apparatus as claimed in claim 1 , wherein the synchronisation logic comprises search logic configured to search the first data stream to detect the data pattern.
8. The apparatus as claimed in claim 1 , wherein the higher-layer decoder is configured to initiate decoding of the first data stream at any arbitrary point within the first data stream.
9. The apparatus as claimed in claim 1 , wherein the first data stream comprises a series of messages, wherein the synchronisation event has a predetermined relationship to a boundary of a message.
10. The apparatus as claimed in claim 1 , wherein the first data stream comprises a series of messages, wherein the synchronisation event determines the position of at least a first message header, wherein the decoding logic is configured to decode a message header before a data packet associated with the message header.
11. The apparatus as claimed in claim 1 , wherein the lower-level protocol is defined by the advanced microcontroller bus architecture specification.
12. The apparatus as claimed in claim 1 , wherein the higher-layer protocol formats the data stream in higher-layer protocol elements and the lower-layer protocol formats the first data stream in lower-layer protocol elements and wherein the boundaries of the higher-layer protocol elements and the lower-layer protocol elements are not aligned.
13. The apparatus as claimed in claim 1 , wherein the first data stream formatted according to the higher-layer protocol comprises a series of messages, wherein each message comprises a header and a packet and wherein the header identifies, according to the higher-layer protocol, the packet length.
14. The apparatus as claimed in claim 13 , wherein the header of a message of the first data stream provides an instruction, according to the higher-layer protocol, as to a location of a next subsequent header in the data stream.
15. The apparatus as claimed in claim 1 , configured as or part of a system on a chip.
16. A method comprising:
decoding a received data stream formatted according to a lower-layer protocol that interleaves portions of a first data stream and one or more additional data streams to produce de-interleaved data streams comprising the first data stream and the one or more additional data streams; and
decoding, using decoding logic, the first data stream formatted according to a higher-layer protocol to produce trace data by
processing the first data stream using synchronization logic to detect a data pattern within the first data stream as a synchronisation event; and
using the synchronisation event to synchronise decoding of the received first data stream to produce the trace data.
17. An apparatus comprising means for performing the method of claim 16 .
18. A computer program that when executed by a processor causes the performance of the method of claim 16 .
19. An apparatus comprising:
a higher-layer encoder configured to receive trace data and produce a first data stream formatted according to a higher-layer protocol, and wherein the higher-layer encoder is configured to add a reserved data sequence to the first data stream in response to trigger events configured by a user; and
a lower-layer encoder configured to receive the first data stream formatted according to the higher-layer protocol and one or more additional data streams and to produce an encoded data stream formatted according to a lower-layer protocol that interleaves portions of the first data stream and the one or more additional data streams.