Integrated circuit with scan chain having dual-edge triggered scannable flip flops and method of operating thereof
View Patent ↗An integrated circuit includes a scan chain, a clock divider circuit, and clock selection circuitry. The scan chain includes a plurality of dual edge flip flops, wherein each dual edge flip flop includes a data input, a scan input, a clock input, and data output. The clock divider circuit is coupled to receive a test clock and is configured to divide the test clock to provide a divided test clock. The clock selection circuitry has a first input coupled to receive the divided test clock, a second input coupled to receive a system clock, a control input coupled to receive a scan enable signal, and an output coupled to provide one of the divided test clock and the system clock as a clock signal to the clock inputs of the scan chain based on the scan enable signal.
1. An integrated circuit comprising:
a scan chain having a first plurality of dual edge flip flops and a second plurality of dual edge flip flops, wherein each dual edge flip flop of the first and second pluralities of dual edge flip flops includes a data input, a scan input, a clock input, and data output, the scan chain to receive a test pattern at the scan input that is synchronous with a test clock during a shift phase of scan testing;
a clock divider circuit coupled to receive the test clock and configured to divide the test clock to provide a divided test clock having a lower frequency than the test clock;
clock selection circuitry having a first input coupled to receive the divided test clock, a second input coupled to receive a system clock, a control input coupled to receive a scan enable signal, and an output coupled to provide one of the divided test clock and the system clock as a clock signal to the clock input of the scan chain based on the scan enable signal, wherein the divided test clock is provided to the clock input of the scan chain during the shift phase of scan testing; and
second clock selection circuitry having a first input coupled to receive the divided test clock, a second input coupled to receive a second system dock, a control input coupled to receive the scan enable signal, and an output configured to provide the divided test clock as a second clock signal to the clock input of each dual edge flip flop of the second plurality of dual edge flip flops when the scan enable signal has the first value, and to provide the second system clock as the clock signal to the clock input of each dual edge flip flop of the second plurality of dual edge flip flops when the scan enable signal has the second value wherein the second system clock is 90 degrees out of phase with the system clock.
2. The integrated circuit of claim 1 , wherein each dual edge flip flop includes a control input configured to receive the scan enable signal, wherein each dual edge flip flop is configured to latch a value in response to the clock signal at one of the scan input or the data input based on the scan enable signal.
3. The integrated circuit of claim 2 , wherein each dual edge flip flop is configured to latch a value at the one of the scan input or the data input in response to each of a rising edge and a falling edge of the clock signal.
4. The integrated circuit of claim 3 , wherein each dual edge flip flop comprises a first latch and a second latch coupled in parallel with the first latch, wherein each dual edge flip flop is configured to provide an output value at the data output from the first latch during a first phase of a clock cycle of the clock signal and from the second latch during a second phase of the clock cycle of the clock signal.
5. The integrated circuit of claim 1 , wherein the clock selection circuitry is configured to provide the divided test clock as the clock signal when the scan enable signal is asserted and to provide the system clock as the clock signal when the scan enable signal is negated.
6. The integrated circuit of claim 5 , each dual edge flip flop is configured to select the scan input when the scan enable signal is asserted and select the data input when the scan enable signal is negated.
7. The integrated circuit of claim 6 , wherein when the scan enable signal is asserted, the scan chain is configured to shift in a scan test pattern, and when the scan enable signal is negated, the scan chain is configured to operate in a functional mode.
8. The integrated circuit of claim 1 , wherein the test clock is received from an external tester.
9. The integrated circuit of claim 1 , wherein the clock divider circuit provides the divided test clock with a frequency that is half a frequency of the test clock.
10. The integrated circuit of claim 1 , wherein a scan input of a first dual edge flip flop of the plurality of dual edge flip flops is coupled to a data output of a second dual edge flip flop of the plurality of dual edge flip flops and a data input of the first dual edge flip flop is coupled to an output of combinational logic.
11. A method for scan testing in an integrated circuit having first scan chain having a first plurality of dual edge flip flops and a second scan chain having a second plurality of dual edge flip flops, the method comprising:
receiving a test clock;
dividing the test clock to generate a divided test clock having a lower frequency than the test clock;
receiving, at a scan input of each dual edge flip flop, of the first plurality of dual edge flip flops, a test pattern that is synchronous with the test clock during a shift phase of scan testing;
providing the divided test clock to a clock input of each dual edge flip flop of the first scan chain during the shift phase of scan testing;
providing a system clock to the clock input of each dual edge flip flop of the scan chain during a capture phase of scan testing;
providing the divided test clock to a clock input of each dual edge flip flop of the second plurality of dual edge flip flops during a shift phase of scan testing;
providing a second system clock to the clock input of each dual edge flip flop of the second plurality of dual edge flip flops during the capture phase of scan testing, wherein the second system clock is 90 degrees out of phase with the system clock; and
during the capture phase, latching values output by combinational logic at a data input of each dual edge flip flop of the second plurality of dual edge flip flops in response to both rising and falling edges of the second system clock.
12. The method of claim 11 , further comprising:
during the shift phase, shifting bits of a test pattern into scan inputs of the dual edge flops of the scan chain in response to both rising and falling edges of the divided test clock.
13. The method of claim 12 , further comprising:
receiving the test clock from a tester; and
receiving the test pattern from the tester, wherein bits of the test pattern received from the tester are aligned to one of falling edges or rising edges of the test clock.
14. The method of claim 12 , further comprising:
during the capture phase, latching values output by combinational logic at a data input of each dual edge flip flop of the first plurality of dual edge flip flops in response to both rising and falling edges of the system clock.
15. The method of claim 12 , wherein dividing the test clock to generate the divided test clock is performed such that the divided test clock has a frequency that is half of a frequency of the test clock.
16. An integrated circuit comprising:
a scan chain having a first plurality of dual edge flip flops and a second plurality of dual edge flip flops, wherein
each dual edge flip flop includes a data input, a scan input, a clock input configured to receive a clock signal, a control input configured to receive a scan enable signal, and a data output, wherein each dual edge flip flop of the first plurality of dual edge flip flops is configured to latch a test pattern bit at the scan input in response to the clock signal when the scan enable signal has a first value and latch a data bit from combinational logic at the data input in response to the clock signal when the scan enable signal has a second value, the scan chain to receive a test pattern at the scan input that is synchronous with a test clock when the scan enable signal has the first value,
each dual edge flip flop of the second plurality of dual edge flip flops includes a data input, a scan input, a clock input configured to receive a second clock signal, a control input configured to receive the scan enable signal, and a data output, wherein each the dual edge flip of the second plurality of dual edge flip flops is configured to latch a test pattern bit at the scan input in response to a second clock signal when the scan enable signal has the first value and latch a data bit from combinational logic at the data input in response to the second clock signal when the scan enable signal has the second value;
a clock divider circuit coupled to receive the test clock and configured to divide the test clock to provide a divided test clock having a lower frequency than the test clock;
first clock selection circuitry having a first input coupled to receive the divided test clock, a second input coupled to receive a system clock, a control input coupled to receive a scan enable signal, and an output configured to provide the divided test clock as the clock signal when the scan enable signal has the first value and to provide the system clock as the clock signal when the scan enable signal has the second value, wherein the divided test clock is provided to the clock input of the scan chain when the scan enable signal has the first value; and
second clock selection circuitry having a first input coupled to receive the divided test clock, a second input coupled to receive a second system clock, a control input coupled to receive the scan enable signal, and an output configured to provide the divided test clock as the second clock signal when the scan enable signal has the first value and to provide the second system clock as the clock signal when the scan enable signal has the second value, wherein the second system clock is 90 degrees out of phase with the system clock.
17. The integrated circuit of claim 16 , wherein each dual edge flip flop is configured to latch test pattern bits in response to rising and falling edges of the clock signal when the scan enable signal has the first value and latch data bits in response to rising and failing edges of the clock signal when the scan enable signal has the second value.
18. The integrated circuit of claim 16 , wherein the scan enable signal has the first value during a shift phase of scan testing and has the second value during a capture phase of scan testing and during a functional mode of the integrated circuit.