Semiconductor device and fabrication method thereof
A semiconductor device includes a gate stack, an isolation structure and a strained feature. The gate stack is over a substrate. The isolation structure is in the substrate. The strained feature is disposed between the gate stack and the isolation structure and disposed in the substrate. The strained feature includes an upper surface adjacent to the isolation structure having a first crystal plane and a sidewall surface adjacent to the gate stack having a second crystal plane. The first crystal plane is different from the second crystal plane.
1. A semiconductor device, comprising:
a gate stack over a substrate;
an isolation structure in the substrate; and
a strained feature disposed between the gate stack and the isolation structure and disposed in the substrate, wherein the strained feature comprises:
an upper surface adjacent to the isolation structure having a first crystal plane; and
a sidewall surface adjacent to the gate stack having a second crystal plane, wherein the first crystal plane is different from the second crystal plane.
2. The device of claim 1 , further comprising:
a contact feature over the strained feature.
3. The device of claim 2 , further comprising:
a cap layer between the strained feature and the contact feature.
4. The device of claim 1 , wherein the first crystal plane is (311).
5. The device of claim 1 , wherein the second crystal plane is (111).
6. The device of claim 1 , further comprising:
an epi Si layer over the strained feature.
7. The device of claim 1 , wherein a top surface of the substrate is disposed above the upper surface of the strained feature.
8. The device of claim 1 , wherein the sidewall surface of the strained feature is not parallel with the upper surface of the strained feature.
9. An integrated circuit, comprising:
a gate over a substrate;
an isolation structure in the substrate;
a strained feature disposed between the gate and the isolation structure and disposed in a wedge-shaped recess cavity in the substrate, wherein the strained feature comprises an uppermost surface not parallel to a top surface of the substrate; and
a cap layer over the strained feature.
10. The integrated circuit of claim 9 , wherein the uppermost surface has a first crystal plane, and wherein the strained feature further comprises:
a sidewall surface adjacent to the gate having a second crystal plane, wherein the first crystal plane is different from the second crystal plane.
11. The integrated circuit of claim 10 , wherein the sidewall surface of the strained feature is not parallel with the uppermost surface of the strained feature.
12. The integrated circuit of claim 11 , wherein the first crystal plane is (311) and the second crystal plane is (111).
13. The integrated circuit of claim 9 , wherein a top surface of the substrate is disposed above or equal to the uppermost surface of the strained feature.
14. The integrated circuit of claim 9 , wherein the cap layer is disposed in the wedge-shaped recess cavity in the substrate.
15. The integrated circuit of claim 9 , further comprising a contact feature over the strained feature.
16. A semiconductor device, comprising:
a first gate stack over a substrate;
an isolation structure in the substrate;
a first strained feature between the first gate stack and the isolation structure and disposed in a recess cavity in the substrate, wherein the first strained feature comprises:
an upper surface adjacent to the isolation structure having a first crystal plane, wherein the upper surface is angled with respect to a top surface of the substrate; and
a sidewall surface adjacent to the first gate stack having a second crystal plane, wherein the first crystal plane is different from the second crystal plane; and
a cap layer over the first strained feature.
17. The semiconductor device of claim 16 , further comprising:
a second gate stack over the substrate; and
a second strained feature between the first gate stack and the second gate stack and in the substrate, wherein the second strained feature comprises an upper surface having a third crystal plane, wherein the first crystal plane is different than the third crystal plane.
18. The semiconductor device of claim 17 , wherein the first crystal plane is (311) or (111) and the third crystal plane is (100).
19. The semiconductor device of claim 16 , wherein the top surface of the substrate is above the upper surface of the first strained feature.
20. The integrated circuit of claim 9 , wherein a surface of the cap layer is planar.