IP Library › Granted Patent US 9,446,941
Granted Patent B2
US 9,446,941 · App. 14/568,845 · Granted Sep 20, 2016

Method of lower profile MEMS package with stress isolations

Inventors: Tongbi Jiang (Santa Clara, CA); Jie-Hua Zhao (Cupertino, CA); Peter G. Hartwell (Sunnyvale, CA)
Assignee: Apple Inc.
B81B7/0058
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Quick Facts
Patent No.
US 9,446,941
App. No.
14/568,845
Granted
Sep 20, 2016
Kind
B2
Abstract

MEMS packages, modules, and methods of fabrication are described. In an embodiment, a MEMS package includes a MEMS die and an IC die mounted on a front side of a surface mount substrate, and a molding compound encapsulating the IC die and the MEMS die on the front side of the surface mount substrate. In an embodiment, a landing pad arrangement on a back side of the surface mount substrate forms and anchor plane area for bonding the surface mount substrate to a module substrate that is not directly beneath the MEMS die.

Claims (22)

1. A module comprising:

a module substrate;

a surface mount substrate bonded to a top side the module substrate with an arrangement of conductive bumps including all conductive bumps bonding the surface mount substrate to the module substrate;

wherein the arrangement of conductive bumps corresponds to an anchored area of the surface mount substrate directly over the module substrate, and the surface mount substrate includes a hanging area that laterally extends from the anchored area in which a conductive bump is not formed directly beneath the hanging area of the surface mount substrate;

an integrated circuit (IC) die mounted on a front side of the surface mount substrate in the anchored area of the surface mount substrate;

a micro-electro-mechanical systems (MEMS) die mounted on the front side of the surface mount substrate in the hanging area of the surface mount substrate;

a molding compound encapsulating the IC die and the MEMS die on the front side of the surface mount substrate.

2. The module of claim 1 , further comprising a trench in a top surface of the molding compound between the IC die and the MEMS die.

3. The module of claim 1 , further comprising a metal trace on the top side of the module substrate directly underneath the hanging area of the surface mount substrate, and a solder mask directly over the metal trace directly underneath the hanging area of the surface mount substrate.

4. The module of claim 1 , further comprising a metal trace on a back side of the surface mount substrate directly in the hanging area of the surface mount substrate, and a solder mask directly on the metal trace directly in the hanging area of the surface mount substrate.

5. The module of claim 1 , wherein the molding compound is formed directly on the surface mount substrate.

6. The module of claim 1 , further comprising a plurality of components bonded to the top side the module substrate, wherein the plurality of components are encapsulated in a second molding compound on the top side of the module substrate.

7. The module of claim 6 , wherein a top surface of the molding compound encapsulating the IC die and the MEMS die is below a top surface of the second molding compound encapsulating the plurality of components.

8. The module of claim 1 , wherein the molding compound encapsulating the IC die and the MEMS die does not cover a top surface of the MEMS die.

9. The module of claim 1 , further comprising:

a bumper on the front side of the module substrate directly beneath the hanging area of the surface mount substrate; and

an air gap directly between a back side of the surface mount substrate and the bumper.

10. The module of claim 1 , further comprising:

a bumper on a back side of the surface mount substrate directly beneath the hanging area of the surface mount substrate; and

an air gap directly between a front side of the module substrate and the bumper.

11. The module of claim 1 , further comprising an opening in the surface mount substrate between the IC die and the MEMS die.

12. The module of claim 1 , further comprising a trench in a top surface of the molding compound between the IC die and the MEMS die, wherein a bottom surface of the trench is below a top surface of the MEMS die.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 12, 2014
From: JIANG, TONGBI; ZHAO, JIE-HUA; HARTWELL, PETER G.
To: APPLE INC.
Reel/Frame 034496/0096 →
Continuity (1)
Related Publication 20160167949A1 · Jun 16, 2016