Granted Patent B2

US 9,281,442 · App. 14/570,521 · Granted Mar 8, 2016

Abstract

Claims (165)

1. A nanowire device, comprising:

a semiconductor nanowire core; and

a first semiconductor shell located radially around the semiconductor nanowire core; and

a second semiconductor shell located radially between the semiconductor nanowire core and the first semiconductor shell;

wherein:

the first semiconductor shell has a non-uniform surface profile having at least 3 peaks;

each of the at least 3 peaks is separated from an adjacent one of the at least 3 peaks by a valley;

each of the at least 3 peaks extends at least 2 nm in a radial direction away from an adjacent valley;

the device comprises a light emitting diode (LED) device and the first semiconductor shell comprises an active region quantum well shell;

the second semiconductor shell has a non-uniform surface profile having at least 3 peaks;

each of the at least 3 peaks is separated from an adjacent one of the at least 3 peaks by a valley; and

each of the at least 3 peaks extends at least 2 nm in a radial direction away from an adjacent valley.

2. The device of claim 1 , wherein the second semiconductor shell comprises an underlayer barrier shell of the active region quantum well.

3. The device of claim 1 , wherein the second semiconductor shell comprises an underlayer shell located radially inward from the active region.

4. The device of claim 1 , wherein:

a radial thickness of the first semiconductor shell varies by at least 15 percent in a nanowire axial direction between the peaks and the valleys;

a peak to adjacent valley separation in the first semiconductor shell in the nanowire axial direction is 10 to 30 nm;

each of the at least 3 peaks in the first semiconductor shell extends 3 to 5 nm in a radial direction away from an adjacent valley;

the first semiconductor shell has a thickness of greater than 5 nm in the radial direction;

a peak to adjacent valley separation in the second semiconductor shell in a nanowire axial direction is 10 to 30 nm; and

each of the at least 3 peaks in the second semiconductor shell extends 3 to 5 nm in a radial direction away from an adjacent valley.

5. The device of claim 1 , further comprising:

an insulating mask layer located over a semiconductor surface of a support, wherein the semiconductor nanowire core comprises a first conductivity type semiconductor nanowire core extending substantially perpendicular from the semiconductor surface of the support through an opening in the insulating mask layer;

at least one second conductivity type semiconductor shell extending over and around the active region quantum well shell;

a first electrode layer that contacts the second conductivity type semiconductor shell; and

a second electrode layer which is electrically connects to the semiconductor nanowire core.

6. The device of claim 5 , wherein:

the first conductivity type comprises n-type;

the second conductivity type comprises p-type;

the support comprises a n-GaN or n-AlGaN n-type semiconductor buffer layer on a substrate;

the semiconductor nanowire core comprises a n-GaN nanowire core;

the active region quantum well shell comprises an InGaN shell between GaN barrier shells; and

the first electrode comprises a transparent conductive oxide (TCO).

7. The device of claim 1 , wherein:

each of the at least 3 peaks in the first semiconductor shell comprises a nanometer scale discontinuity along an m-plane of the first semiconductor shell that projects at least partially along a p-plane; and

the active quantum well shell comprises an In(Al)GaN semiconductor shell which contains indium rich regions located at the peaks having at least 5 atomic percent higher indium content than indium poor regions located at the valleys.

8. The device of claim 7 , wherein the active quantum well shell comprises an InGaN semiconductor shell in which the indium rich regions contain more than 10 atomic percent indium and the indium poor regions contain less than 10 atomic percent indium.

9. The device of claim 8 , wherein indium rich regions contain 15 to 30 atomic percent indium and the indium poor regions contain 1 to 5 atomic percent indium.

10. The device of claim 9 , wherein the LED has a 495 to 590 nm peak emission wavelength or a 591 to 650 nm peak emission wavelength.

11. The device of claim 10 , wherein the LED has an about 520 nm peak emission wavelength and the indium rich regions contain about 20 atomic percent indium.

12. The device of claim 10 , wherein the LED has an about 610 nm peak emission wavelength and the indium rich regions contain about 30 atomic percent indium.

13. A light emitting diode (LED) device, comprising:

a semiconductor nanowire core; and

a first semiconductor shell comprising an In(Al)GaN active region quantum well shell located radially around the semiconductor nanowire core,

wherein:

the active region quantum well shell contains indium rich regions having at least 5 atomic percent higher indium content than indium poor regions in the active region quantum well shell; and

wherein the indium rich regions comprise integral portions of the active region quantum well shell rather than discrete nanoparticles embedded in the active region quantum well shell.

14. The device of claim 13 , wherein the active quantum well shell comprises an InGaN semiconductor shell in which the indium rich regions contain more than 10 atomic percent indium and the indium poor regions contain less than 10 atomic percent indium.

15. The device of claim 14 , wherein indium rich regions contain 15 to 30 atomic percent indium and the indium poor regions contain 1 to 5 atomic percent indium.

16. The device of claim 15 , wherein the LED has a 495 to 590 nm peak emission wavelength or a 591 to 650 nm peak emission wavelength.

17. The device of claim 16 , wherein the LED has an about 520 nm peak emission wavelength and the indium rich regions contain about 20 atomic percent indium.

18. The device of claim 16 , wherein the LED has an about 610 nm peak emission wavelength and the indium rich regions contain about 30 atomic percent indium.

19. The device of claim 13 , wherein:

the first semiconductor shell has a non-uniform surface profile having at least 3 peaks which comprise the indium rich regions;

each of the at least 3 peaks is separated from an adjacent one of the at least 3 peaks by a valley which comprises the indium poor region; and

each of the at least 3 peaks extends at least 2 nm in a radial direction away from an adjacent valley.

20. The device of claim 19 , further comprising a second semiconductor shell located radially between the semiconductor nanowire core and the first semiconductor shell.

21. The device of claim 20 , wherein:

the second semiconductor shell has a non-uniform surface profile having at least 3 peaks;

each of the at least 3 peaks is separated from an adjacent one of the at least 3 peaks by a valley; and

each of the at least 3 peaks extends at least 2 nm in a radial direction away from an adjacent valley.

22. The device of claim 21 , wherein the second semiconductor shell comprises an underlayer barrier shell of the active region quantum well.

23. The device of claim 21 , wherein the second semiconductor shell comprises an underlayer shell located radially inward from the active region.

24. The device of claim 21 , wherein:

a radial thickness of the first semiconductor shell varies by at least 15 percent in a nanowire axial direction between the peaks and the valleys.

a peak to adjacent valley separation in the first semiconductor shell in the nanowire axial direction is 10 to 30 nm;

each of the at least 3 peaks in the first semiconductor shell extends 3 to 5 nm in a radial direction away from an adjacent valley;

the first semiconductor shell has a thickness of greater than 5 nm in the radial direction;

a peak to adjacent valley separation in the second semiconductor shell in a nanowire axial direction is 10 to 30 nm; and

each of the at least 3 peaks in the second semiconductor shell extends 3 to 5 nm in a radial direction away from an adjacent valley.

25. The device of claim 21 , further comprising:

an insulating mask layer located over a semiconductor surface of a support, wherein the semiconductor nanowire core comprises a first conductivity type semiconductor nanowire core extending substantially perpendicular from the semiconductor surface of the support through an opening in the insulating mask layer;

at least one second conductivity type semiconductor shell extending over and around the active region quantum well shell;

a first electrode layer that contacts the second conductivity type semiconductor shell; and

a second electrode layer which is electrically connects to the semiconductor nanowire core.

26. The device of claim 25 , wherein:

the first conductivity type comprises n-type;

the second conductivity type comprises p-type;

the support comprises a n-GaN or n-AlGaN n-type semiconductor buffer layer on a substrate;

the semiconductor nanowire core comprises a n-GaN nanowire core;

the active region quantum well shell comprises an InGaN shell between GaN barrier shells; and

the first electrode comprises a transparent conductive oxide (TCO).

27. The device of claim 21 , wherein each of the at least 3 peaks in the first semiconductor shell comprises a nanometer scale discontinuity along an m-plane of the first semiconductor shell that projects at least partially along a p-plane.

28. A method of making nanowire device, comprising:

forming a semiconductor nanowire core;

forming a first semiconductor shell located radially around the semiconductor nanowire core; and

forming a second semiconductor shell radially around the semiconductor nanowire core prior to forming the first semiconductor shell;

wherein:

the first semiconductor shell has a non-uniform surface profile having at least 3 peaks;

each of the at least 3 peaks is separated from an adjacent one of the at least 3 peaks by a valley;

each of the at least 3 peaks extends at least 2 nm in a radial direction away from an adjacent valley;

the device comprises a light emitting diode (LED) device and the first semiconductor shell comprises an active region quantum well shell;

the second semiconductor shell has a non-uniform surface profile having at least 3 peaks;

each of the at least 3 peaks is separated from an adjacent one of the at least 3 peaks by a valley;

each of the at least 3 peaks extends at least 2 nm in a radial direction away from an adjacent valley; and

the first semiconductor shell is formed on the second semiconductor shell and assumes the non-uniform surface profile of the second semiconductor shell.

29. The method of claim 28 , wherein the second semiconductor shell comprises an underlayer barrier shell of the active region quantum well.

30. The method of claim 28 , wherein the second semiconductor shell comprises an underlayer shell located radially inward from the active region.

31. The method of claim 28 , wherein:

a radial thickness of the first semiconductor shell varies by at least 15 percent in a nanowire axial direction between the peaks and the valleys;

a peak to adjacent valley separation in the first semiconductor shell in the nanowire axial direction is 10 to 30 nm;

each of the at least 3 peaks in the first semiconductor shell extends 3 to 5 nm in a radial direction away from an adjacent valley;

the first semiconductor shell has a thickness of greater than 5 nm in the radial direction;

a peak to adjacent valley separation in the second semiconductor shell in a nanowire axial direction is 10 to 30 nm; and

each of the at least 3 peaks in the second semiconductor shell extends 3 to 5 nm in a radial direction away from an adjacent valley.

32. The method of claim 28 , further comprising:

forming an insulating mask layer located over a semiconductor surface of a support, wherein forming the semiconductor nanowire core comprises epitaxially growing a first conductivity type semiconductor nanowire core extending substantially perpendicular from the semiconductor surface of the support through an opening in the insulating mask layer;

forming at least one second conductivity type semiconductor shell extending over and around the active region quantum well shell;

forming a first electrode layer that contacts the second conductivity type semiconductor shell; and

forming a second electrode layer which is electrically connects to the semiconductor nanowire core.

33. The method of claim 32 , wherein:

the first conductivity type comprises n-type;

the second conductivity type comprises p-type;

the support comprises a n-GaN or n-AlGaN n-type semiconductor buffer layer on a substrate;

the semiconductor nanowire core comprises a n-GaN nanowire core;

the active region quantum well shell comprises an InGaN shell between GaN barrier shells; and

the first electrode comprises a transparent conductive oxide (TCO).

34. The method of claim 28 , wherein:

each of the at least 3 peaks in the first semiconductor shell comprises a nanometer scale discontinuity along an m-plane of the first semiconductor shell that projects at least partially along a p-plane; and

the active quantum well shell comprises an In(Al)GaN semiconductor shell which contains indium rich regions located at the peaks having at least 5 atomic percent higher indium content than indium poor regions located at the valleys.

35. The method of claim 34 , wherein the active quantum well shell comprises an InGaN semiconductor shell in which the indium rich regions contain more than 10 atomic percent indium and the indium poor regions contain less than 10 atomic percent indium.

36. The method of claim 35 , wherein indium rich regions contain 15 to 30 atomic percent indium and the indium poor regions contain 1 to 5 atomic percent indium.

37. The method of claim 36 , wherein the LED has a 495 to 590 nm peak emission wavelength or a 591 to 650 nm peak emission wavelength.

38. The method of claim 37 , wherein the LED has an about 520 nm peak emission wavelength and the indium rich regions contain about 20 atomic percent indium.

39. The method of claim 37 , wherein the LED has an about 610 nm peak emission wavelength and the indium rich regions contain about 30 atomic percent indium.

40. A method of making a light emitting diode (LED) device, comprising:

forming a semiconductor nanowire core; and

forming a first semiconductor shell radially around the semiconductor nanowire core, the first semiconductor shell comprising an In(Al)GaN active region quantum well shell with indium rich regions which are integrally formed in-situ during the formation of the first semiconductor shell,

wherein indium rich regions having at least 5 atomic percent higher indium content than indium poor regions in the first semiconductor shell.

41. The method of claim 40 , wherein the active quantum well shell comprises an InGaN semiconductor shell in which the indium rich regions contain more than 10 atomic percent indium and the indium poor regions contain less than 10 atomic percent indium.

42. The method of claim 41 , wherein indium rich regions contain 15 to 30 atomic percent indium and the indium poor regions contain 1 to 5 atomic percent indium.

43. The method of claim 42 , wherein the LED has a 495 to 590 nm peak emission wavelength or a 591 to 650 nm peak emission wavelength.

44. The method of claim 43 , wherein the LED has an about 520 nm peak emission wavelength and the indium rich regions contain about 20 atomic percent indium.

45. The method of claim 43 , wherein the LED has an about 610 nm peak emission wavelength and the indium rich regions contain about 30 atomic percent indium.

46. The method of claim 40 , wherein:

the first semiconductor shell has a non-uniform surface profile having at least 3 peaks which comprise the indium rich regions;

each of the at least 3 peaks is separated from an adjacent one of the at least 3 peaks by a valley which comprises the indium poor region; and

each of the at least 3 peaks extends at least 2 nm in a radial direction away from an adjacent valley.

47. The method of claim 46 , further comprising forming a second semiconductor shell radially around the semiconductor nanowire core prior to forming the first semiconductor shell.

48. The method of claim 47 , wherein:

the second semiconductor shell has a non-uniform surface profile having at least 3 peaks;

each of the at least 3 peaks is separated from an adjacent one of the at least 3 peaks by a valley; and

each of the at least 3 peaks extends at least 2 nm in a radial direction away from an adjacent valley.

49. The method of claim 48 , wherein the second semiconductor shell comprises an underlayer barrier shell of the active region quantum well.

50. The method of claim 48 , wherein the second semiconductor shell comprises an underlayer shell located radially inward from the active region.

51. The method of claim 48 , wherein:

a radial thickness of the first semiconductor shell varies by at least 15 percent in a nanowire axial direction between the peaks and the valleys;

a peak to adjacent valley separation in the first semiconductor shell in the nanowire axial direction is 10 to 30 nm;

each of the at least 3 peaks in the first semiconductor shell extends 3 to 5 nm in a radial direction away from an adjacent valley;

the first semiconductor shell has a thickness of greater than 5 nm in the radial direction;

a peak to adjacent valley separation in the second semiconductor shell in a nanowire axial direction is 10 to 30 nm; and

each of the at least 3 peaks in the second semiconductor shell extends 3 to 5 nm in a radial direction away from an adjacent valley.

52. The method of claim 48 , further comprising:

forming an insulating mask layer located over a semiconductor surface of a support, wherein forming the semiconductor nanowire core comprises epitaxially growing a first conductivity type semiconductor nanowire core extending substantially perpendicular from the semiconductor surface of the support through an opening in the insulating mask layer;

forming at least one second conductivity type semiconductor shell extending over and around the active region quantum well shell;

forming a first electrode layer that contacts the second conductivity type semiconductor shell; and

forming a second electrode layer which is electrically connects to the semiconductor nanowire core.

53. The method of claim 52 , wherein:

the first conductivity type comprises n-type;

the second conductivity type comprises p-type;

the support comprises a n-GaN or n-AlGaN n-type semiconductor buffer layer on a substrate;

the semiconductor nanowire core comprises a n-GaN nanowire core;

the active region quantum well shell comprises an InGaN shell between GaN barrier shells; and

the first electrode comprises a transparent conductive oxide (TCO).

54. The method of claim 48 , wherein each of the at least 3 peaks in the first semiconductor shell comprises a nanometer scale discontinuity along an m-plane of the first semiconductor shell that projects at least partially along a p-plane.

Assignments (10)