Sequential access assembly strip test adapter
An assembly strip test method and adapter allows for the concurrent loading of multiple assembly strips for testing in a concurrent and/or round-robin fashion in a strip tester. The test method and adapter allows the multiple assembly strips to be loaded into a strip tester in a single load cycle, reducing assembly strip load cycle overhead. Signals generated by test probes can be used to select between the loaded assembly strips for testing via the strip tester. Parallel coupling between corresponding pins of corresponding integrated circuits of different assembly strips allows a single test probe to be used as stimulus or monitor for two or more assembly strips. In certain configurations a stackable assembly strip test adapter is used. In other configurations the integrated circuits include at least part of the assembly strip selection decoding logic.
1. An assembly strip test adapter, comprising:
at least first and second sites for respectively mounting at least first and second assembly strips, each assembly strip having a plurality of integrated circuits, wherein test points for the integrated circuits of the first assembly strip are adapted to contact corresponding test probes of a strip tester; and
electrical coupling between the test points for the integrated circuits of the first assembly strip and corresponding test points for the integrated circuits of the second assembly strip, wherein:
a first test point for a first integrated circuit of the first assembly strip is adapted to receive a signal from a first test probe of the strip tester; and
the electrical coupling is adapted to convey the signal from the first test point to a second test point for a second integrated circuit of the second assembly strip, wherein the signal is adapted to be first used for testing the first assembly strip via the strip tester during a first test cycle and then used for testing the second assembly strip via the strip tester during a second test cycle.
2. The test adapter of claim 1 , wherein:
the electrical coupling includes at least one signal logic inverter;
the first test point is a chip select for the first integrated circuit;
the second test point is a chip select for the second integrated circuit;
the signal is coupled from the first test probe to the chip select for the first integrated circuit;
the signal is also coupled to the logic inverter; and
the output of the logic inverter is coupled to the chip select for the second integrated circuit, such that:
when the signal is at a first level during the first test cycle, the first integrated circuit is selected for testing and the second integrated circuit is de-selected; and
when the signal is at a second level, different from the first level, during the second test cycle, the first integrated circuit is de-selected and the second integrated circuit is selected for testing.
3. The test adapter of claim 1 , wherein:
the test adapter provides N sites for mounting N assembly strips, N>2;
the test adapter provides contact for at least two test probes dedicated to assembly strip selection;
signals from the at least two test probes are used to drive a one-of-N decoder of the first integrated circuit; and
outputs of the one-of-N decoder are used to select between the N assembly strips for testing.
4. The test adapter of claim 1 , wherein:
the test adapter comprises a plurality of via probes, each via probe comprising a lower probe head and an upper probe head electrically interconnected by the electrical coupling;
the lower probe heads form the first site for mounting the first assembly strip on a lower side of the test adapter; and
the upper probe heads form the second site for mounting the second assembly strip on an upper side of the test adapter.
5. The test adapter of claim 1 , where the test adapter is adapted to be used with a strip tester test bed comprising a two-dimensional matrix of test probes whose locations on the strip tester test bed correspond to locations of the test points for the integrated circuits of the first assembly strip.
6. The test adapter of claim 1 , wherein the test adapter is adapted to be loaded with the first and second assembly strips prior to the first test cycle for the first assembly strip.
7. The test adapter of claim 1 , where the first site for mounting the first assembly strip is substantially on top of the second site for mounting the second assembly strip such that mounting the first and second assembly strips corresponds roughly to stacking the first and second assembly strips.
8. The test adapter of claim 1 , wherein the first integrated circuit includes integral distributed assembly strip selection decoding logic, the logic used to receive the signal received from the first test probe and contribute to the selection of the first assembly strip for testing.
9. An assembly strip testing method, comprising:
providing at least first and second sites for respectively mounting at least first and second assembly strips in an assembly strip test adapter, each assembly strip having a plurality of integrated circuits, wherein test points for the integrated circuits of the first assembly strip contact corresponding test probe of a strip tester; and
providing electrical coupling between the test points for integrated circuits of the first assembly strip and corresponding test points for the integrated circuits of the second assembly strip,
wherein:
a first test point for a first integrated circuit of the first assembly strip receives a signal from a first test probe of the strip tester; and
the electrical coupling conveys the signal from the first test point to a second test point for a second integrated circuit of the second assembly strip, wherein the signal is first used for testing the first assembly strip via the strip tester during a first test cycle and then used for testing the second assembly strip via the strip tester during a second test cycle.
10. The assembly strip testing method of claim 9 , comprising:
including at least one signal logic inverter within the electrical coupling, wherein:
the first test point is a chip select for the first integrated circuit; and
the second test point is a chip select for the second integrated circuit;
coupling the signal from the first test probe to the chip select for the first integrated circuit;
coupling the signal to the logic inverter; and
coupling the output of the logic inverter to the chip select for the second integrated circuit, such that:
when the signal is at a first level during the first test cycle, the first integrated circuit is selected for testing and the second integrated circuit is de-selected; and
when the signal is at a second level, different from the first level, during the second test cycle, the first integrated circuit is de-selected and the second integrated circuit is selected for testing.
11. The assembly strip testing method of claim 9 , comprising:
providing the test adapter with N sites for mounting N assembly strips, N>2;
providing contact via the test adapter for at least two test probes dedicated to assembly strip selection;
using signals from the at least two test probes to drive a one-of-N decoder of the first integrated circuit; and
using the outputs of the one-of-N decoder to select between the N assembly strips for testing.
12. The assembly strip testing method of claim 9 , comprising:
providing the test adapter comprising a plurality of via probes, each via probe comprising a lower probe head and an upper probe head electrically interconnected by the electrical coupling, wherein:
the lower probe heads form the first site for mounting the first assembly strip on a lower side of the test adapter; and
the upper probe heads form the second site for mounting the second assembly strip on an upper side of the test adapter.
13. The assembly strip testing method of claim 9 , comprising using the test adapter to couple the test adapter to a strip tester test bed comprising a two-dimensional matrix of test probes whose locations on the strip tester test bed correspond to locations of the test points for the integrated circuits of each assembly strip.
14. The assembly strip testing method of claim 9 , wherein the test adapter is loaded with the first and second assembly strips prior to the first test cycle for the first assembly strip.
15. The assembly strip testing method of claim 9 , wherein the first site for mounting the first assembly strip is substantially on top of the second site for mounting the second assembly strip such that mounting the first and second assembly strips corresponds roughly to stacking the first and second assembly strips.
16. The assembly strip testing method of claim 9 , wherein the first integrated circuit includes integral distributed assembly strip selection decoding logic, wherein the logic is used to receive the signal received from the first test probe and contribute to the selection of the first assembly strip for testing.