Direct memory access (DMA) unit with error detection
Systems and methods for self-checking a direct memory access system are disclosed. These may include generating a check sum value associated with a first job of the plurality of jobs, the first job comprising a read job; if a first predetermined check value is available, comparing the first check sum value with the first predetermined check value; generating a second check sum value associated with a last job of the plurality of jobs, the last job comprising a write job; if a second predetermined check value is available, comparing the second check sum value with the second predetermined check value; and if the second predetermined check value is not available, comparing the first check sum value with the second check sum value.
1. A method for self-checking within direct memory access (DMA) system, the method comprising:
for a job chain comprising a plurality of jobs, wherein each of the plurality of jobs comprises a source memory address, a destination memory address, an effective data length, a job chain identifier, and a mode identifier:
generating a first check sum value for read data associated with a first job of the plurality of jobs, the first job comprising a read operation by a read data engine of the DMA to obtain the read data from a source memory address associated with the first job;
if the mode identifier associated with the first job indicates that a first predetermined check value is available, comparing the first check sum value with the first predetermined check value;
generating a second check sum value for write data associated with a last job of the plurality of jobs, the last job comprising a write operation of the write data by a write data engine of the DMA to a destination memory address associated with the last job;
if the mode identifier associated with the last job indicates that a second predetermined check value is available, comparing the second check sum value with the second predetermined check value; and
if the mode identifier associated with the last job does not indicate that the second predetermined check value is available, comparing the first check sum value with the second check sum value.
2. The method of claim 1 , further comprising checking an effective read data length for the first job to ensure that it is the same as an effective write data length for the last job.
3. The method of claim 1 , further comprising setting an error bit if the first check sum value is different from the second check sum value.
4. The method of claim 1 , further comprising setting an error bit if the first check sum value is different from the first predetermined check value.
5. The method of claim 1 , further comprising setting an error bit if the second check sum value is different from the second predetermined check value.
6. The method of claim 1 , wherein at least one of the job chains in the plurality of job chains further comprises an intermediate job, the intermediate job executed between the first job and the last job.
7. The method of claim 6 , wherein the source address associated with the intermediate job is associated with data stored in a plurality of nonconsecutive memory locations.
8. The method of claim 6 , wherein the destination address associated with the intermediate job is associated with data stored in a plurality of nonconsecutive memory locations.
9. The method of claim 1 , further comprising, for each job chain in the plurality of job chains:
checking an address alignment for the first job in the job chain to ensure that it is the same as an address alignment for the last job in the job chain;
generating a third check sum value associated with a first address associated with the first job;
generating a fourth check sum value associated with a second address associated with the last job; and
comparing the third check sum value with the fourth check sum value.
10. A method for self-checking a direct memory access (DMA) system, the method comprising:
for a job chain comprising a plurality of jobs, wherein each of the plurality of jobs comprises a source memory address, a destination memory address, an effective data length, a job chain identifier, and a mode identifier:
generating a first check sum value associated with a first address associated with a first job of the plurality of jobs, the first job comprising a read operation from the first address by a read data engine of the DMA;
if the mode identifier associated with the first job indicates that a first predetermined check value is available, comparing the first check sum value with the first predetermined check value;
generating a second check sum value associated with a second address associated with a last job of the plurality of jobs, the last job comprising a write operation to the second address by a write data engine of the DMA;
if the mode identifier associated with the last job indicates that a second predetermined check value is available, comparing the second check sum value with the second predetermined check value; and
if the mode identifier associated with the last job does not indicate that the second predetermined check value is available, comparing the first check sum value with the second check sum value.
11. The method of claim 10 , further comprising checking an address alignment for the first job to ensure that it is the same as an address alignment for the last job.
12. The method of claim 10 , further comprising setting an error bit if the first check sum value is different from the second check sum value.
13. The method of claim 10 , further comprising setting an error bit if the first check sum value is different from the first predetermined check value.
14. The method of claim 10 , further comprising setting an error bit if the second check sum value is different from the second predetermined check value.
15. A system for self-checking within a direct memory access (DMA) system, the system comprising:
a transaction scheduler operable to schedule a job chain comprising a plurality of jobs, wherein each of the plurality of jobs comprises a source memory address, a destination memory address, an effective data length, a job chain identifier, and a mode identifier;
a read data engine operable to perform read operations;
a write data engine operable to perform write operations;
a read data check unit communicatively coupled to the transaction scheduler, the read data check unit operable to:
generate a first check sum value associated with data associated with a first job of the plurality of jobs, the first job comprising a read operation; and
if the mode identifier associated with the first job indicates that a first predetermined check value is available, comparing the first check sum value with the first predetermined check value; and
a write data check unit communicatively coupled to the transaction scheduler, the write data check unit operable to:
generate a second check sum value associated with data associated with a last job of the plurality of jobs, the last job comprising a write operation;
if the mode identifier associated with the last job indicates that a second predetermined check value is available, comparing the second check sum value with the second predetermined check value; and
if the mode identifier associated with the last job does not indicate that the second predetermined check value is available, comparing the first check sum value with the second check sum value.
16. The system of claim 15 , wherein the write data check unit is further operable to set an error bit if the first check sum value is different from the second check sum value.
17. The system of claim 15 , wherein the read data check unit is further operable to set an error bit if the first check sum value is different from the first predetermined check value.
18. The system of claim 15 , wherein the write data check unit is further operable to set an error bit if the second check sum value is different from the second predetermined check value.
19. The system of claim 15 , wherein the source address associated with at least one of the plurality of jobs is associated with data stored in a plurality of nonconsecutive memory locations.
20. The system of claim 15 , further comprising:
a read address check unit operable to:
generate a third check sum value associated with a first address associated with the first job; and
a write address check unit operable to:
generate a fourth check sum value associated with a second address associated with the last job; and
compare the third check sum value with the fourth check sum value.