IP Library Granted Patent US 9,184,257
Granted Patent B2
US 9,184,257 · App. 14/575,204 · Granted Nov 10, 2015

Semiconductor device and related fabrication methods

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Quick Facts
Patent No.
US 9,184,257
App. No.
14/575,204
Granted
Nov 10, 2015
Kind
B2
Abstract

Semiconductor device structures and related fabrication methods are provided. An exemplary semiconductor device structure includes a collector region of semiconductor material having a first conductivity type, a base region of semiconductor material within the collector region, the base region having a second conductivity type opposite the first conductivity type, and a doped region of semiconductor material having the second conductivity type, wherein the doped region is electrically connected to the base region and the collector region resides between the base region and the doped region. In exemplary embodiments, the dopant concentration of the doped region is greater than a dopant concentration of the collector region to deplete the collector region as the electrical potential of the base region exceeds that of the collector region.

Claims (47)

1. A method of fabricating a bipolar transistor on a semiconductor substrate, the method comprising:

forming a first region of semiconductor material having a first conductivity type in the semiconductor substrate;

forming a collector region of semiconductor material having a second conductivity type opposite the first conductivity type overlying the first region;

forming a second region of semiconductor material having the first conductivity type that abuts the first region;

forming a base region of semiconductor material having the first conductivity type within the collector region of semiconductor material; and

providing an electrical connection between the base region and the second region, the electrical connection resulting in the base region and the second region having the same electrical potential.

2. The method of claim 1 , wherein forming the collector region comprises forming the collector region having a dopant concentration that is less than a dopant concentration of the first region.

3. The method of claim 1 , wherein a dopant concentration of the first region is greater than a dopant concentration of the collector region.

4. The method of claim 1 , the semiconductor substrate comprising a support layer of semiconductor material, a buried layer of dielectric material overlying the support layer, and a second layer of semiconductor material overlying the buried layer, wherein forming the first region comprises forming the first region in the second layer.

5. The method of claim 1 , wherein:

forming the collector region comprises forming an epitaxial layer of semiconductor material having the second conductivity type on the first region; and

forming the second region comprises implanting, into the epitaxial layer, ions having the first conductivity type and a dopant concentration greater than a dopant concentration of the epitaxial layer.

6. The method of claim 1 , the semiconductor substrate comprising a silicon-on-insulator substrate including a layer of semiconductor material overlying an insulating layer, wherein:

forming the first region comprises implanting ions having the first conductivity type into the layer of semiconductor material; and

forming the collector region comprises forming an epitaxial layer of semiconductor material having the second conductivity type on the first region.

7. The method of claim 6 , wherein forming the epitaxial layer of semiconductor material comprises epitaxially growing, on the first region, in-situ doped semiconductor material having a dopant concentration that is less than a dopant concentration of the first region.

8. The method of claim 7 , wherein forming the second region comprises implanting, into the epitaxial layer, ions having the first conductivity type and a dopant concentration greater than the dopant concentration of the epitaxial layer.

9. A method of fabricating a bipolar transistor on a semiconductor substrate, the method comprising:

forming a buried region having a first conductivity type in the semiconductor substrate;

forming a collector region overlying the buried region, the collector region having a second conductivity type opposite the first conductivity type;

forming a base region within the collector region, the base region having the first conductivity type, wherein at least a first portion of the collector region resides between the base region and the buried region; and

forming a sinker region having the first conductivity type in the semiconductor substrate, wherein:

the sinker region abuts the buried region; and

at least a second portion of the collector region resides between the sinker region and the base region; and

providing an electrical connection between the base region and the sinker region, the electrical connection resulting in the base region and the sinker region having the same electrical potential.

10. The method of claim 9 , wherein forming the sinker region comprises forming the sinker region laterally surrounding the collector region.

11. The method of claim 9 , wherein forming the collector region comprises forming the collector region having a dopant concentration that is less than a dopant concentration of the buried region within the buried region.

12. The method of claim 11 , wherein forming the collector region comprises forming the collector region having the dopant concentration that is less than a dopant concentration of the sinker region.

13. The method of claim 9 , wherein:

forming the collector region comprises implanting ions having the second conductivity type and a first dopant concentration into the layer of semiconductor material; and

forming the sinker region comprises implanting ions having the first conductivity type and a second dopant concentration into the semiconductor substrate, wherein the first dopant concentration is less than the second dopant concentration.

14. The method of claim 9 , further comprising forming an emitter region having the second conductivity type within the base region.

15. A method of fabricating a semiconductor device on a semiconductor substrate, the method comprising:

forming a first region of semiconductor material having a first conductivity type in the semiconductor substrate;

forming a collector region having a second conductivity type overlying the first region, the second conductivity type being opposite the first conductivity type;

forming a sinker region laterally surrounding the collector region and abutting the first region in the semiconductor substrate, the sinker region having the first conductivity type;

forming a base region having the first conductivity type within the collector region, at least a first portion of the collector region residing between the sinker region and the base region and at least a second portion of the collector region residing between the base region and the first region;

forming an emitter region having the second conductivity type within the base region; and

providing an electrical connection between the base region and the sinker region, the electrical connection resulting in the base region and the sinker region having the same electrical potential.

16. The method of claim 15 , wherein:

forming the collector region comprises forming an epitaxial layer of semiconductor material having the second conductivity type on the first region; and

forming the sinker region comprises implanting, into the epitaxial layer, ions having the first conductivity type and a dopant concentration greater than a dopant concentration of the epitaxial layer.

17. The method of claim 15 , the semiconductor substrate comprising a silicon-on-insulator substrate including a layer of semiconductor material overlying an insulating layer, wherein:

forming the first region comprises implanting ions having the first conductivity type into the layer of semiconductor material; and

forming the collector region comprises forming an epitaxial layer of semiconductor material having the second conductivity type on the first region.

18. The method of claim 17 , wherein forming the epitaxial layer of semiconductor material comprises epitaxially growing, on the first region, in-situ doped semiconductor material having a dopant concentration that is less than a dopant concentration of the first region.

19. The method of claim 18 , wherein forming the second region comprises implanting, into the epitaxial layer, ions having the first conductivity type and a dopant concentration greater than the dopant concentration of the epitaxial layer.

Assignments (14)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
MERGER Recorded Jan 3, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041144/0363 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037444/0444 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037444/0535 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037358/0001 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Feb 18, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 035033/0001 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Feb 18, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 035034/0019 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Feb 18, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 035033/0923 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 18, 2014
From: LIN, XIN; BLOMBERG, DANIEL J.; ZUO, JIANG-KAI
To: FREESCALE SEMICONDUCTOR INC.
Reel/Frame 034548/0296 →