III-V MOSFETs with halo-doped bottom barrier layer
Techniques for controlling short channel effects in III-V MOSFETs through the use of a halo-doped bottom (III-V) barrier layer are provided. In one aspect, a method of forming a MOSFET device is provided. The method includes the steps of: forming a III-V barrier layer on a substrate; forming a III-V channel layer on a side of the III-V barrier layer opposite the substrate, wherein the III-V barrier layer is configured to confine charge carriers in the MOSFET device to the III-V channel layer; forming a gate stack on a side of the III-V channel layer opposite the III-V barrier layer; and forming halo implants in the III-V barrier layer on opposite sides of the gate stack. A MOSFET device is also provided.
1. A method of forming a metal-oxide semiconductor field effect transistor (MOSFET) device, the method comprising the steps of:
forming a III-V barrier layer on a substrate;
forming a III-V channel layer on a side of the III-V barrier layer opposite the substrate, wherein the III-V barrier layer is configured to confine charge carriers in the MOSFET device to the III-V channel layer;
forming a gate stack on a side of the III-V channel layer opposite the III-V barrier layer;
forming halo implants in the III-V barrier layer on opposite sides of the gate stack;
forming source and drain extension implants in the III-V channel layer on the opposite sides of the gate stack; and
removing portions of the III-V channel layer and portions of the source and drain extension implants adjacent to the opposite sides of the gate stack thereby exposing underlying portions of the III-V barrier layer on the opposite sides of the gate stack,
wherein the step of forming the source and drain extension implants and the step of removing the portions of the III-V channel layer and the portions of the source and drain extension implants are performed before the step of forming the halo implants.
2. The method of claim 1 , further comprising the step of:
using shallow trench isolation (STI) to define at least one active area in the III-V channel layer.
3. The method of claim 1 , wherein the gate stack comprises a gate dielectric, a gate metal layer on the gate dielectric, and a semiconductor gate layer on a side of the gate metal layer opposite the gate dielectric.
4. The method of claim 1 , wherein the III-V barrier layer comprises a first III-V material and the channel layer comprises a second III-V material, and wherein the first III-V material has a wider band gap than the second III-V material.
5. The method of claim 1 , wherein the portions of the III-V channel layer and portions of the source and drain extension implants adjacent to opposite sides of the gate stack are removed using an anisotropic etching process wherein the III-V barrier layer acts as an etch stop.
6. The method of claim 1 , further comprising the step of:
forming spacers on opposite sides of the gate stack,
wherein the step of forming the spacers is performed before the step of removing the portions of the III-V channel layer and the portions of the source and drain extension implants.
7. The method of claim 1 , further comprising the steps of:
forming raised source and drain regions on the III-V barrier layer adjacent to the III-V channel layer on the opposite sides of the gate stack; and
forming source and drain contacts on each of the raised source and drain regions.