Disposable pillars for contact formation
Sacrificial plugs for forming contacts in integrated circuits, as well as methods of forming connections in integrated circuit arrays are disclosed. Various pattern transfer and etching steps can be used to create densely-packed features and the connections between features. A sacrificial material can be patterned in a continuous zig-zag line pattern that crosses word lines. Planarization can create parallelogram-shaped blocks of material that can overlie active areas to form sacrificial plugs, which can be replaced with conductive material to form contacts.
1. An integrated circuit comprising:
a plurality of word lines;
a plurality of conductive plugs comprising, as seen in plan view, blocks of conductive material with a nonrectangular, parallelogram footprint, the blocks of conductive material flanked on a first pair of opposite sides by two of the word lines and flanked on a second pair of opposite sides by blocks of insulating material;
a plurality of memory storage devices overlying the conductive plugs; and
a plurality of active areas underlying the conductive plugs,
wherein each of the plurality of memory storage devices is contacted by a block of conductive material so as to provide an electrical connection to at least one of the active areas.
2. The integrated circuit of claim 1 , wherein the non-rectangular, parallelogram footprint is a rhomboid footprint.
3. The integrated circuit of claim 1 , wherein the non-rectangular, parallelogram footprint has at least two interior angles of between approximately 20 and approximately 30 degrees.
4. The integrated circuit of claim 1 , wherein the non-rectangular, parallelogram footprint has at least two interior angles of between approximately 40 and approximately 50 degrees.
5. The integrated circuit of claim 1 , wherein the blocks of conductive material are associated with a plan view pattern, the pattern comprising:
first columns, each first column comprising one of the word lines;
second columns alternating regularly with the first columns, each second column comprising the blocks of conductive material, which alternate up and down each of the second columns with the blocks of insulating material, the second columns arranged in ascending and descending trios, wherein:
the ascending trios each comprise three sequential second columns having blocks of conductive material with parallelogram footprints, each parallelogram footprint having a top edge parallel to a bottom edge, wherein the top and bottom edges of the parallelogram slope upwardly to the right, and each top edge is aligned with the top edge of two other blocks of conductive material in other second columns in the ascending trios; and
the descending trios each comprise three sequential second columns having blocks of conductive material with parallelogram footprints, each parallelogram footprint having a top edge parallel to a bottom edge, wherein the top and bottom edges of the parallelogram slope downwardly to the right, and each top edge is aligned with the top edge of two other blocks of conductive material in other second columns in the descending trios.
6. The integrated circuit of claim 5 , wherein the slope of the top and bottom edges of the parallelogram footprints in the ascending trios intersects with the slope of the top and bottom edges of the parallelogram footprints in the descending trios at an angle in the range of between 45 and 179 degrees.
7. The integrated circuit of claim 6 , wherein the angle is about 130 degrees.
8. The integrated circuit of claim 1 , wherein the underlying active areas are oval shaped.
9. The integrated circuit of claim 1 , wherein the underlying active areas comprise one source region and two drain regions, and at least two word lines contact the source region.
10. The integrated circuit of claim 1 , wherein the blocks of conductive material comprise cell contacts from the plurality of memory devices to the underlying active areas.
11. The integrated circuit of claim 1 , further comprising a plurality of bit lines overlying the active areas.
12. An integrated circuit comprising:
a plurality of substantially parallel first interconnect lines;
a plurality of conductive plugs comprising, as seen in plan view, blocks of conductive material with a nonrectangular, parallelogram footprint, the blocks of conductive material flanked on a first pair of opposite sides by two of the interconnect lines and flanked on a second pair of opposite sides by blocks of insulating material;
a plurality of active areas underlying the conductive plugs; and
a plurality of drain regions overlying the plurality conductive plugs,
wherein each of the blocks of conductive material is configured to contact at least one of the active areas and provide an electrical connection to at least one drain region.
13. The integrated circuit of claim 12 , wherein the blocks of connective material comprise cell contacts.
14. The integrated circuit of claim 12 , wherein the first interconnect lines comprise word lines.
15. The integrated circuit of claim 12 , wherein the non-rectangular, parallelogram footprint is a rhomboid footprint.
16. The integrated circuit of claim 12 , wherein the non-rectangular, parallelogram footprint has at least two interior angles of between approximately 20 and approximately 30 degrees.
17. The integrated circuit of claim 12 , wherein the non-rectangular, parallelogram footprint has at least two interior angles of between approximately 40 and approximately 50 degrees.
18. The integrated circuit of claim 12 , wherein the blocks of conductive material are associated with a plan view pattern, the pattern comprising:
first columns, each first column comprising one of the word lines;
second columns alternating regularly with the first columns, each second column comprising the blocks of conductive material, which alternate up and down each of the second columns with the blocks of insulating material, the second columns arranged in ascending and descending trios, wherein:
the ascending trios each comprise three sequential second columns having blocks of conductive material with parallelogram footprints, each parallelogram footprint having a top edge parallel to a bottom edge, wherein the top and bottom edges of the parallelogram slope upwardly to the right, and each top edge is aligned with the top edge of two other blocks of conductive material in other second columns in the ascending trios; and
the descending trios each comprise three sequential second columns having blocks of conductive material with parallelogram footprints, each parallelogram footprint having a top edge parallel to a bottom edge, wherein the top and bottom edges of the parallelogram slope downwardly to the right, and each top edge is aligned with the top edge of two other blocks of conductive material in other second columns in the descending trios.
19. The integrated circuit of claim 12 , wherein the underlying active areas are oval shaped.
20. The integrated circuit of claim 12 , wherein the underlying active areas comprise one source region and two drain regions, and at least two word lines contact the source region.