IP Library Granted Patent US 9,275,982
Granted Patent B2
US 9,275,982 · App. 14/591,551 · Granted Mar 1, 2016

Method of forming interconnection structure of package structure

Inventors: Chia-Yen Lee (Taoyuan, TW); Hsin-Chang Tsai (Taoyuan, TW); Peng-Hsin Lee (Taoyuan, TW)
Assignee: DELTA ELECTRONICS, INC.
H01L25/50H01L21/768H01L21/76877H01L21/76898H01L23/481H01L25/0657H01L25/074H01L25/18H01L24/03H01L24/05H01L24/13H01L24/16H01L24/81H01L2224/02372H01L2224/0332H01L2224/0401H01L2224/05009H01L2224/0557H01L2224/05147H01L2224/05548H01L2224/06181H01L2224/131H01L2224/13024H01L2224/13147H01L2224/16146H01L2224/16148H01L2224/81193H01L2224/81815H01L2924/00014H01L2924/12042
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Quick Facts
Patent No.
US 9,275,982
App. No.
14/591,551
Granted
Mar 1, 2016
Kind
B2
Abstract

A package structure including: a first semiconductor device including a first semiconductor substrate and a first electronic device, the first semiconductor device having a first side and a second side, wherein at least part of the first electronic device being adjacent to the first side, and the first semiconductor device has a via-hole formed through the first semiconductor device, wherein the via-hole has a first opening adjacent to the first side; an interconnection structure disposed in the first semiconductor device, wherein the interconnection structure includes: a via structure disposed in the via-hole without exceeding the first opening; a first pad disposed on the first side of the first semiconductor device and covering the via-hole; and a second semiconductor device vertically integrated with the first semiconductor device.

Claims (22)

1. A method of forming a package structure comprising:

providing a first semiconductor device having a first side and a second side opposite to to the first side;

forming a via-hole through the first semiconductor device, wherein the via-hole has a first opening neighboring the first side and a second opening neighboring the second side;

forming a first pad covering the first opening;

forming a via structure in the via-hole subsequent to forming the first pad, wherein the via structure comprises a conductive material and is adjoined to the first pad; and

substantially vertically integrating the first semiconductor device with a second semiconductor device.

2. The method of forming the package structure as claimed in claim 1 , further comprising:

forming a second pad covering the second opening and adjoined with the via structure.

3. The method of forming the package structure as claimed in claim 1 , wherein the first semiconductor device comprising:

a first semiconductor substrate;

a first electronic device disposed on the first semiconductor substrate, at least part of the first electronic device being adjacent to the first side of the first semiconductor device; and

a passivation layer disposed on the first semiconductor substrate and the first electronic device.

4. The method of forming the package structure as claimed in claim 3 , wherein the second semiconductor device has a third side and a fourth side opposite to the third side, and the second semiconductor device comprises a second semiconductor substrate and a second electronic device disposed on the second semiconductor substrate, at least part of the second electronic device being adjacent to the third side.

5. The method of forming the package structure as claimed in claim 4 , wherein the first semiconductor device is vertically integrated with the second semiconductor device while the first side of the first semiconductor device and the third side of the second semiconductor device face each other.

6. The method of forming the package structure as claimed in claim 4 , wherein the first semiconductor device is vertically integrated with the second semiconductor device while the second side of the first semiconductor device and the third side of the second semiconductor device face each other.

7. The method of forming the package structure as claimed in claim 4 , wherein the first semiconductor device is vertically integrated with the second semiconductor device while the second side of the first semiconductor device and the fourth side of the second semiconductor device face each other.

8. The method of forming the package structure as claimed in claim 4 , wherein the first semiconductor device is vertically integrated with the second semiconductor device while the first side of the first semiconductor device and the fourth side of the second semiconductor device face each other.

9. The method of forming the package structure as claimed in claim 1 , wherein the forming of the first pad comprises performing a screen printing process to form the first pad covering the first opening.

10. The method of forming the package structure as claimed in claim 1 , wherein the first semiconductor device comprising:

a first semiconductor substrate;

a first electronic device disposed on the first semiconductor substrate and at least part of the first electronic device being adjacent to the second side of the first semiconductor device; and

a passivation layer disposed on the first semiconductor substrate and thefirst electronic device.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 16, 2025
From: ANCORA SEMICONDUCTORS, INC.
To: MARE INFINITUS TECHNOLOGIES LLC
Reel/Frame 071720/0332 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 8, 2022
From: DELTA ELECTRONICS, INC.
To: ANCORA SEMICONDUCTORS INC.
Reel/Frame 061695/0106 →
Continuity (3)
Division 14020045 · Sep 6, 2013
Continuation In Part 13675297 · Nov 13, 2012
Related Publication 20150125995A1 · May 7, 2015