Apparatuses and methods including error correction code organization

1. An apparatus comprising:

first memory cells located on a first level of a memory device;

second memory cells located on a second level of the memory device; and

a controller to cause data to be stored in a first memory cell group of the first memory cells, to cause a first portion of an error correction code associated with the data to be stored in a second memory cell group of the first memory cells, to cause additional data to be stored in a first memory cell group of the second memory cells and to cause a second portion of the error correction code to be stored in a second memory cell group of the second memory cells, wherein the controller is further configured to cause at least a portion of an error correction code associated with the additional data to be stored in a third memory cell group of the second memory cells concurrently with storing of the second portion of the error correction code in the second memory cell group of the second memory cells.

2. The apparatus of claim 1 , wherein the controller is further configured to cause an additional portion of the error correction code associated with the data to be stored in a third memory cell group of the first memory cells.

3. The apparatus of claim 1 , wherein the data includes a page of information, and the error correction code is associated with the page of information.

4. The apparatus of claim 1 , further comprising a first line access to access the first memory cells, and a second access line to access the second memory cells.

5. The apparatus of claim 4 , wherein the first access line is located immediately next to the second access line.

6. The apparatus of claim 1 , wherein the first and second memory cells are located on a semiconductor die, and the controller is located on another semiconductor die.

7. The apparatus of claim 1 , wherein the controller includes an error correction code generator to generate the first and second portions of the error correction code.

8. An apparatus comprising:

first memory cells associated with a first access line;

second memory cells associated with a second access line; and

a controller to:

store first data in the first memory cells;

store second data in a first memory cell group of second memory cells;

store at least a portion of an error correction code associated with the second data in a second memory cell group of the second memory cells; and

store a portion of an error correction code associated with the first data in a third memory cell group of the second memory cells, wherein the controller is configured to concurrently store the at least a portion of the error correction code associated with the second data and the portion of the error correction code associated with the first data.

9. The apparatus of claim 8 , wherein the controller is further configured to store at least a portion of an error correction code associated with third data in the second memory cell group of the second memory cells.

10. The apparatus of claim 9 , wherein the controller is further configured to store an additional portion of the error correction code associated with the third data in the third memory cell group of the second memory cells.

11. The apparatus of claim 10 , wherein the portion of the error correction code associated with the first data is stored in the third memory cell group of the second memory cells before the additional portion of the error correction code associated with the third data is stored in the third memory cell group of the second memory cells.

12. The apparatus of claim 8 , wherein the at least a portion of the error correction code associated with the second data and the portion of the error correction code associated with the first data have difference sizes.

13. An apparatus comprising:

first memory cells associated with a first access line;

second memory cells associated with a second access line; and

a controller to:

retrieve information from the first memory cells;

generate data from the information using a first portion of error correction code associated with the data, the first portion of error correction code associated with the data being included in the information;

retrieve a second portion of the error correction code associated with the data from the second memory cells if the data is unsuccessfully generated from the information using the first portion of error correction code associated with the data; and

generate data using the first portion of error correction code associated with the data and the second portion of error correction code associated with the data.

14. The apparatus of claim 13 , wherein the first portion of the error correction code associated with the data and the second portion of the error correction code associated with the data have unequal sizes.

15. The apparatus of claim 13 , wherein the controller is configured to generate the first and second portions of the error correction code based on the data before the information is stored.

16. The apparatus of claim 15 , wherein the first and second memory cells are located on a memory device, and the controller is located on a memory controller.

17. The apparatus of claim 13 , wherein the first and second memory cells and the controller are located on a same semiconductor die.

18. The apparatus claim 13 , wherein the first and second memory cells and the controller are located different semiconductor dice.