MOS-gated power devices, methods, and integrated circuits
MOS-gated devices, related methods, and systems for vertical power and RF devices including an insulated trench and a gate electrode. A body region is positioned so that a voltage bias on the gate electrode will cause an inversion layer in the body region. Permanent electrostatic charges are included in said insulation material. A conductive shield layer is positioned above the insulated trench, to reduce parasitic capacitances.
1. A substantially vertical device comprising:
an insulated trench having a sidewall;
a gate electrode;
a lightly doped diffusion layer adjacent to said sidewall of said insulated trench such that a voltage bias applied to the gate electrode can induce inversion in said lightly doped diffusion layer to thereby create a channel;
intentionally introduced permanent electrostatic charge positioned near said sidewall; and
a conductive shield layer which is positioned above said insulated trench, and not electrically connected to said gate.
2. The vertical device of claim 1 , wherein said gate electrode comprise a plurality of gate electrodes and wherein said gate electrodes are positioned horizontally displaced from said insulated trench.
3. The device of claim 1 , built in a semiconductor structure which includes an epitaxial layer over an N+ buried layer over a P+ substrate, wherein said buried layer is contacted by a sinker diffusion.
4. A substantially vertical device comprising:
a first-conductivity-type source region;
a second-conductivity-type body region separating said source region from a drain region;
a gate electrode positioned such that when a voltage bias is applied to said gate electrode, an inversion region is induced in said body region;
a vertical insulation trench through said body region; and
a first-conductivity-type lightly-doped diffusion in said body region along the sidewalls of said vertical insulation trench.
5. The vertical device of claim 4 , further comprising permanent electrostatic charge positioned along an exterior edge within said vertical insulation trench.
6. The vertical device of claim 4 , wherein said vertical insulation trench is positioned between two gate electrodes and further comprising a shield electrode between said gate electrodes and above said vertical insulation trench.
7. The vertical device of claim 4 , wherein said body region includes a punch-through diffusion between the source region and the lightly-doped diffusion.
8. The vertical device of claim 4 , wherein said gate electrode includes a silicide layer.
9. The device of claim 4 , built in a semiconductor structure which includes an epitaxial layer over an N+ buried layer over a P+ substrate, wherein said buried layer is contacted by a sinker diffusion.
10. A vertical device comprising:
a first-conductivity-type source region;
a second-conductivity-type body region separating said source region from a drain region;
a gate electrode positioned such that when a voltage bias is applied to said gate electrode, an inversion region is induced in said body region;
a vertical insulation trench through said body region;
intentionally introduced permanent electrostatic charge positioned along an exterior edge within said vertical insulation trench, and
a first-conductivity-type lightly-doped diffusion in said body region along the sidewalls of said vertical insulation trench.
11. The vertical device of claim 10 , wherein said vertical insulation trench is positioned between two gate electrodes and further comprising a shield electrode between said gate electrodes and above said vertical insulation trench.
12. The vertical device of claim 10 , wherein said body region includes a punch-through diffusion between the source region and the lightly-doped diffusion.
13. The vertical device of claim 10 , wherein said gate electrode includes a silicide layer.