Vertical GaN JFET with low gate-drain capacitance and high gate-source capacitance
View Patent ↗An embodiment of a vertical power device includes a III-nitride substrate, a drift region coupled to the III-nitride substrate and comprising a III-nitride material of a first conductivity type, and a channel region coupled to the drift region and comprising a III-nitride material of the first conductivity type. The vertical power device also includes a source region coupled to the channel region and comprising a III-nitride material of the first conductivity type, and a gate region coupled to the channel region. The gate region includes a III-nitride material of a second conductivity type. The vertical power device further includes a source-coupled region coupled to the drift region and electrically connected with the source region. The source-coupled region includes a III-nitride material of the second conductivity type.
1. A method comprising:
providing a III-nitride substrate;
forming a channel region and a drift region, wherein:
the drift region and the channel region comprise a III-nitride material of a first conductivity type, and
the drift region is coupled to the III-nitride substrate;
forming a source region coupled to the channel region;
forming a gate region coupled to the channel region, wherein the gate region comprises a III-nitride material of a second conductivity type;
forming a source-coupled region coupled to the drift region; and
electrically connecting the source-coupled region to the source region.
2. The method of claim 1 wherein an area defined by a junction of the gate region and the drift region is smaller than an area defined by a junction of the source-coupled region and the drift region.
3. The method of claim 1 wherein forming either or both of the channel region or the drift region comprises:
forming a III-nitride epitaxial layer coupled to the III-nitride substrate; and
removing at least a portion of the III-nitride epitaxial layer.
4. The method of claim 1 further comprising forming an edge termination structure surrounding the gate region, the source-coupled region, and the channel region.
5. The method of claim 1 wherein:
the gate region and the source-coupled region are formed such that a gap is disposed between the gate region and the source-coupled region; and
the gap has a width smaller than a width of the channel region.
6. The method of claim 1 further comprising forming a p-ohmic contact layer electrically coupled to the source-coupled region.
7. The method of claim 6 further comprising forming a dielectric layer coupled to the p-ohmic contact layer.
8. The method of claim 7 further comprising forming a gate electrode such that:
the gate electrode is electrically connected to the gate region; and
the dielectric layer is disposed between at least a portion of the p-ohmic contact layer and at least a portion of the gate electrode.
9. The method of claim 1 wherein electrically connecting the source-coupled region to the source region comprises forming at least one metal layer coupled to the source-coupled region and the source region.
10. The method of claim 1 wherein the drift region and the channel region are formed from a single III-nitride epitaxial layer.
11. The method of claim 1 further comprising forming a source electrode such that a dielectric layer is disposed between at least a portion of the source region and at least a portion of the source electrode.
12. A method comprising:
providing a III-nitride substrate;
forming a first III-nitride epitaxial layer coupled to the III-nitride substrate;
forming a source region coupled to the first III-nitride epitaxial layer;
removing at least a portion of the first III-nitride epitaxial layer and at least a portion of the source region to form a channel region, a drift region, and a separation region;
forming a second III-nitride epitaxial layer coupled to the channel region and the drift region, the second III-nitride epitaxial layer comprising a gate region and a source-coupled region, wherein the gate region and the source-coupled region are separated by the separation region; and
forming a metal structure electrically connecting the source region with the source-coupled region.
13. The method of claim 12 further comprising forming an Ohmic metal contact coupled to the source-coupled region, wherein the metal structure is coupled to the Ohmic metal contact.
14. The method of claim 12 further comprising:
forming a dielectric layer; and
forming a second metal structure;
wherein:
the second metal structure is electrically connected to the gate region; and
the dielectric layer is disposed between at least a portion of the source-coupled region and at least a portion of the second metal structure.
15. The method of claim 12 wherein:
the gate region is coupled to the drift region at a first area of a surface of the drift region; and
the source-coupled region is coupled to the drift region at a second area of the surface of the drift region, the second area being larger than the first area.
16. The method of claim 12 further comprising forming an edge termination structure surrounding the source-coupled region, the gate region, and the channel region.
17. The method of claim 12 wherein:
the gate region and the source-coupled region are formed such that a gap is disposed between the gate region and the source-coupled region; and
the gap has a width smaller than a width of the channel region.
18. The method of claim 12 further comprising a drain electrode electrically coupled to the III-nitride substrate.