IP Library Granted Patent US 9,564,409
Granted Patent B2
US 9,564,409 · App. 14/606,667 · Granted Feb 7, 2017

Methods of forming semiconductor packages with an intermetallic layer comprising tin and at least one of silver, copper or nickel

Inventors: Michael J. Seddon (Gilbert, AZ); Francis J. Carney (Mesa, AZ)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H01L24/11H01L21/6836H01L21/78H01L23/482H01L24/05H01L24/13H01L24/16H01L24/29H01L24/32H01L24/94H01L21/4825H01L24/03H01L24/17H01L24/27H01L24/81H01L24/83H01L2221/68327H01L2221/68381H01L2224/0345H01L2224/0347H01L2224/0348H01L2224/03416H01L2224/03418H01L2224/03444H01L2224/03452H01L2224/03462H01L2224/03464H01L2224/0401H01L2224/04026H01L2224/05075H01L2224/05082H01L2224/05083H01L2224/05147H01L2224/05155H01L2224/05166H01L2224/05171H01L2224/05639H01L2224/05647H01L2224/11462H01L2224/11464H01L2224/11849H01L2224/1308H01L2224/13111H01L2224/13139H01L2224/13147H01L2224/13155H01L2224/13166H01L2224/13171H01L2224/16227H01L2224/16503H01L2224/16507H01L2224/17106H01L2224/2908H01L2224/29111H01L2224/29139H01L2224/29147H01L2224/29155H01L2224/29166H01L2224/29171H01L2224/32225H01L2224/32245H01L2224/32503H01L2224/8181H01L2224/81439H01L2224/81815H01L2224/81825H01L2224/8381H01L2224/83439H01L2224/83815H01L2224/83825H01L2224/8481H01L2224/8581H01L2224/8681H01L2224/94H01L2924/00015H01L2924/01327H01L2924/10162H01L2924/12041
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Quick Facts
Patent No.
US 9,564,409
App. No.
14/606,667
Granted
Feb 7, 2017
Kind
B2
Abstract

A method of forming a semiconductor package. Implementations include forming on a die backside an intermediate metal layer having multiple sublayers, each including a metal selected from the group consisting of titanium, nickel, copper, silver, and combinations thereof. A tin layer is deposited onto the intermediate metal layer and is then reflowed with a silver layer of a substrate to form an intermetallic layer having a melting temperature above 260 degrees Celsius and including an intermetallic consisting of silver and tin and/or an intermetallic consisting of copper and tin. Another method of forming a semiconductor package includes forming a bump on each of a plurality of exposed pads of a top side of a die, each exposed pad surrounded by a passivation layer, each bump including an intermediate metal layer as described above and a tin layer coupled to the intermediate metal layer is reflowed to form an intermetallic layer.

Claims (31)

1. A method of forming a semiconductor package, comprising:

forming an intermediate metal layer onto a die, the intermediate metal layer comprising a plurality of sublayers coupled to each other, each sublayer comprising a metal selected from the group consisting of titanium, nickel, copper, silver, and any combination thereof;

depositing a tin layer onto the intermediate metal layer; and

reflowing at least a portion of the intermediate layer and the tin layer with a silver layer of a substrate to form an intermetallic layer having a melting temperature greater than 260 degrees Celsius;

wherein prior to reflowing the portion of the intermediate layer and the tin layer with the silver layer:

the substrate comprises the silver layer and a copper layer and no metal layers coupled between the silver layer and the copper layer, and;

the copper layer is not coupled directly with a nickel layer.

2. The method of claim 1 , wherein the substrate comprises a copper layer coupled to the silver layer of the substrate prior to reflowing the tin layer with the silver layer of the substrate.

3. The method of claim 1 , wherein the plurality of sublayers of the intermediate metal layer includes a sublayer comprising titanium and a sublayer comprising nickel.

4. The method of claim 3 , wherein the plurality of sublayers of the intermediate metal layer includes a sublayer comprising silver.

5. The method of claim 4 , wherein the plurality of sublayers includes the following arrangement of the plurality of sublayers: a sublayer comprising titanium formed directly onto the die, a sublayer comprising nickel deposited directly onto the sublayer comprising titanium, and a sublayer comprising silver deposited directly onto the sublayer comprising nickel.

6. The method of claim 1 , wherein the intermetallic layer comprises an intermetallic consisting of silver and tin.

7. The method of claim 1 , wherein one of no solder paste and no solder preform is used during the method of forming the semiconductor package.

8. The method of claim 1 , wherein forming the intermediate metal layer onto the die comprises forming a bump on each of a plurality of exposed pads of the die, where each exposed pad is surrounded by a passivation layer on the top side of the die.

9. The method of claim 1 , wherein the intermetallic layer comprises an intermetallic consisting of copper and tin.

10. A method of forming a semiconductor package, comprising:

forming an intermediate metal layer onto a die backside, the intermediate metal layer comprising a plurality of sublayers coupled to each other, each sublayer comprising a metal selected from the group consisting of titanium, nickel, copper, silver, and any combination thereof;

depositing a tin layer onto the intermediate metal layer; and

reflowing at least a portion of the intermediate layer and the tin layer with a silver layer of a substrate to form an intermetallic layer having a melting temperature greater than 260 degrees Celsius;

wherein the plurality of sublayers of the intermediate metal layer includes a sublayer comprising copper, a sublayer comprising titanium, and a sublayer comprising nickel.

11. The method of claim 10 , wherein the plurality of sublayers includes the following arrangement of the plurality of sublayers: a sublayer comprising titanium formed directly onto the die backside, a sublayer comprising nickel deposited directly onto the sublayer comprising titanium, and a sublayer comprising copper deposited directly onto the sublayer comprising nickel.

12. The method of claim 10 , wherein the plurality of sublayers of the intermediate metal layer includes a sublayer comprising silver.

13. The method of claim 12 , wherein the plurality of sublayers includes the following arrangement of the plurality of sublayers: a sublayer comprising titanium formed directly onto the die backside, a sublayer comprising nickel deposited directly onto the sublayer comprising titanium, a sublayer comprising copper deposited directly onto the sublayer comprising nickel, and a sublayer comprising silver deposited directly onto the sublayer comprising copper.

14. A method of forming a semiconductor package, comprising:

forming an intermediate metal layer onto a die backside, the intermediate metal layer comprising a plurality of sublayers coupled to each other, each sublayer comprising a metal selected from the group consisting of titanium, nickel, copper, silver, and any combination thereof;

depositing a tin layer onto the intermediate metal layer; and

reflowing at least a portion of the intermediate layer and the tin layer with a silver layer of a substrate to form an intermetallic layer having a melting temperature greater than 260 degrees Celsius;

wherein the plurality of sublayers of the intermediate metal layer includes a sublayer comprising titanium and a sublayer comprising copper.

15. The method of claim 14 , wherein the plurality of sublayers includes the following arrangement of the plurality of sublayers: a sublayer comprising titanium formed directly onto the die backside, and a sublayer comprising copper deposited directly onto the sublayer comprising titanium.

16. The method of claim 14 , wherein the plurality of sublayers of the intermediate metal layer includes a sublayer comprising silver.

17. The method of claim 16 , wherein the plurality of sublayers includes the following arrangement of the plurality of sublayers: a sublayer comprising titanium formed directly onto the die backside, a sublayer comprising copper deposited directly onto the sublayer comprising titanium, and a sublayer comprising silver deposited directly onto the sublayer comprising copper.

Assignments (4)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 27, 2015
From: SEDDON, MICHAEL J; CARNEY, FRANCIS J
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 034823/0391 →
Continuity (1)
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