Vertical gallium nitride JFET with gate and source electrodes on regrown gate
View Patent ↗A semiconductor structure includes a GaN substrate with a first surface and a second surface. The GaN substrate is characterized by a first conductivity type and a first dopant concentration. A first electrode is electrically coupled to the second surface of the GaN substrate. The semiconductor structure further includes a first GaN epitaxial layer of the first conductivity type coupled to the first surface of the GaN substrate and a second GaN layer of a second conductivity type coupled to the first GaN epitaxial layer. The first GaN epitaxial layer comprises a channel region. The second GaN epitaxial layer comprises a gate region and an edge termination structure. A second electrode coupled to the gate region and a third electrode coupled to the channel region are both disposed within the edge termination structure.
1. A method of manufacturing a vertical junction field effect transistor (VJFET), the method comprising:
providing a III-nitride substrate;
forming a first III-nitride layer coupled to the substrate, wherein the first III-nitride layer has a first conductivity type;
after forming the first III-nitride layer, forming a plurality of gate projections in a second III-nitride layer, wherein the second III-nitride layer has a second conductivity type;
after forming the gate projections, forming a plurality of channel regions in the first III-nitride layer, wherein the channel regions are interleaved with the gate projections; and
forming a plurality of source regions in a third III-nitride layer, wherein the third III-nitride layer has the first conductivity type, and wherein each of the source regions is coupled to one of the channel regions.
2. The method of claim 1 , wherein forming the channel regions comprises epitaxially growing the channel regions in the first III-nitride layer.
3. The method of claim 1 , further comprising forming an edge termination structure surrounding the channel regions, the gate projections, and the source regions.
4. The method of claim 1 , wherein a drain is at least partly formed by a portion of the III-nitride substrate.
5. The method of claim 1 , wherein:
the III-nitride substrate comprises GaN;
the first III-nitride layer comprises GaN;
the second III-nitride layer comprises GaN; and
the third III-nitride layer comprises GaN.
6. The method of claim 1 , further comprising:
forming a source electrode electrically connected to the source regions;
forming a gate electrode electrically connected to the gate projections; and
forming a drain electrode electrically connected to the III-nitride substrate.
7. The method of claim 6 , wherein the drain electrode is coupled a first side of the III-nitride substrate, wherein the source electrode is coupled to a second side of the III-nitride substrate, and wherein the second side of the III-nitride substrate is opposite the first side of the III-nitride substrate.
8. The method of claim 6 , wherein the drain electrode is directly connected to the III-nitride substrate.
9. The method of claim 6 , further comprising connecting the source electrode to the source regions via a plurality of contacts.
10. The method of claim 6 , further comprising connecting the gate electrode to the gate projections via a continuous portion of the second III-nitride layer.
11. A vertical junction field effect transistor (VJFET) formed by a method comprising:
providing a III-nitride substrate;
forming a first III-nitride layer coupled to the substrate, wherein the first III-nitride layer has a first conductivity type;
after forming the first III-nitride layer, forming a plurality of gate projections in a second III-nitride layer, wherein the second III-nitride layer has a second conductivity type,
after forming the gate projections, forming a plurality of channel regions in the first III-nitride layer, wherein the channel regions are interleaved with the gate projections; and
forming a plurality of source regions in a third III-nitride layer, wherein the third III-nitride layer has the first conductivity type, and wherein each of the source regions is coupled to one of the channel regions.
12. The VJFET of claim 11 , wherein forming the channel regions comprises epitaxially growing the channel regions in the first III-nitride layer.
13. The VJFET of claim 11 , wherein the method further comprises forming an edge termination structure surrounding the channel regions, the gate projections, and the source regions.
14. The VJFET of claim 11 , wherein a drain is at least partly formed by a portion of the III-nitride substrate.
15. The VJFET of claim 11 , wherein:
the III-nitride substrate comprises GaN;
the first III-nitride layer comprises GaN;
the second III-nitride layer comprises GaN; and
the third III-nitride layer comprises GaN.
16. The VJFET of claim 11 , wherein the method further comprises:
forming a source electrode electrically connected to the source regions;
forming a gate electrode electrically connected to the gate projections; and
forming a drain electrode electrically connected to the III-nitride substrate.
17. The VJFET of claim 16 , wherein the drain electrode is coupled a first side of the III-nitride substrate, wherein the source electrode is coupled to a second side of the III-nitride substrate, and wherein the second side of the III-nitride substrate is opposite the first side of the III-nitride substrate.
18. The VJFET of claim 16 , wherein the drain electrode is directly connected to the III-nitride substrate.
19. The VJFET of claim 16 , wherein the method further comprises connecting the source electrode to the source regions via a plurality of contacts.
20. The VJFET of claim 16 , wherein the method further comprises connecting the gate electrode to the gate projections via a continuous portion of the second III-nitride layer.