MAKING AN EFUSE

1 . A wafer chip, comprising:

a first fuse having a first critical dimension formed in a layer of the wafer chip; and

a second fuse having a second critical dimension formed in the layer of the wafer chip;

wherein the first fuse and the second fuse are configured to burn out at different applied voltages.

2 . The wafer chip of claim 1 wherein the first fuse is formed by applying a first mask to the layer to create a first channel in the layer having the first critical dimension and the second fuse is formed by applying a second mask to the layer to create a second channel in the layer having a second critical dimension.

3 . The wafer chip claim 2 , further comprising applying light having a first property to the first mask and applying light having a second property to the second mask.

4 . The wafer chip of claim 3 , wherein the first property and the second property further comprise at least one of: a frequency of the light; an intensity of the light; and a duration of exposure of the light.

5 . The wafer chip of claim 1 , further wherein the first and second critical dimension further comprise at least one of a width and a cross-sectional area.

6 . The wafer chip of claim 1 , wherein the first fuse is configured to control a first set of transistors in the layer and the second fuse is configured to control a second set of transistors in the layer.

7 . The wafer chip of claim 1 , wherein at least one of the first fuse and the second fuse are configured to be burned out after a packaging stage of a manufacturing process of the chip to design the chip.