IP Library Granted Patent US 9,659,837
Granted Patent B2
US 9,659,837 · App. 14/610,115 · Granted May 23, 2017

Direct bonded copper semiconductor packages and related methods

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Quick Facts
Patent No.
US 9,659,837
App. No.
14/610,115
Granted
May 23, 2017
Kind
B2
Abstract

A power semiconductor package includes a first direct bonded copper (DBC) substrate having a plurality of connection traces on a first face of the first DBC substrate. A plurality of die are coupled to the connection traces, each die coupled to one of the connection traces at a first face of the die. A second DBC substrate includes connection traces on a first face of the second DBC substrate. A second face of each die is coupled to one of the connection traces of the first face of the second DBC substrate. A cavity between the first face of the first DBC substrate and the first face of the second DBC substrate is filled with an encapsulating compound. Terminal pins may be coupled to connection traces on the first face of the first DBC substrate. More than two DBC substrates may be stacked to form a stacked power semiconductor package.

Claims (20)

1. A method of forming a power semiconductor package, comprising:

coupling a first face of each of a plurality of die with one of a plurality of connection traces of a first face of a first direct bonded copper (DBC) substrate using sintering paste;

coupling a second face of each of the plurality of die with one of a plurality of connection traces of a first face of a second DBC substrate using sintering paste, wherein the first DBC substrate and second DBC substrate each comprise a double DBC substrate comprising a ceramic plate sandwiched between a first copper layer and a second copper layer, wherein the first copper layer of the first DBC substrate comprises the connection traces of the first DBC substrate and wherein the first copper layer of the second DBC substrate comprises the connection traces of the second DBC substrate;

sintering the sintering paste using heat and pressure; and

filling a cavity between the first face of the first DBC substrate and the first face of the second DBC substrate with an encapsulating compound forming a power semiconductor package.

2. The method of claim 1 , wherein the sintering paste is a silver sintering paste.

3. The method of claim 1 , wherein the encapsulating compound is a silicone gel and wherein filling the cavity comprises applying a vacuum at a first end of the cavity while dispensing the encapsulating compound at a second end of the cavity.

4. The method of claim 1 , further comprising coupling each of a plurality of terminal pins to one of the connection traces of the first face of the first DBC substrate.

5. A method of forming a power semiconductor package, comprising:

coupling a first face of each of a first plurality of die with one of a plurality of connection traces of a first face of a first direct bonded copper (DBC) substrate using sintering paste;

coupling a second face of each of the first plurality of die with one of a plurality of connection traces of a first face of a second DBC substrate using sintering paste;

coupling a first face of each of a second plurality of die with one of a plurality of connection traces of a second face of the second DBC substrate using sintering paste;

coupling a second face of each of the second plurality of die with one of a plurality of connection traces of a first face of a third DBC substrate using sintering paste;

sintering the sintering paste using heat and pressure;

filling a first cavity between the first face of the first DBC substrate and the first face of the second DBC substrate, and filling a second cavity between the second face of the second DBC substrate and the first face of the third DBC substrate with an encapsulating compound, and;

coupling each of a plurality of terminal pins to one of the connection traces of the first face of the first DBC substrate to form a semiconductor package.

6. The method of claim 5 , further comprising coupling a first face of each of a third plurality of die with one of a plurality of connection traces of a second face of the third DBC substrate using sintering paste.

7. The method of claim 5 , wherein the sintering paste is a silver sintering paste.

8. The method of claim 5 , wherein the encapsulating compound is a silicone gel.

9. The method of claim 5 , wherein the first DBC substrate and second DBC substrate each comprise a double DBC substrate comprising a ceramic plate sandwiched between a first copper layer and a second copper layer.

Assignments (4)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 30, 2015
From: TOLENTINO, ERIK NINO; MANIKAM, VEMAL RAJA; ARIPIN, AZHAR
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 034854/0622 →