IP Library Granted Patent US 9,368,389
Granted Patent B2
US 9,368,389 · App. 14/612,672 · Granted Jun 14, 2016

Semiconductor device with voids within silicon-on-insulator (SOI) structure and method of forming the semiconductor device

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Quick Facts
Patent No.
US 9,368,389
App. No.
14/612,672
Granted
Jun 14, 2016
Kind
B2
Abstract

A semiconductor device with voids within a silicon-on-insulator (SOI) structure and a method of forming the semiconductor device are provided. Voids are formed within a Buried Oxide layer (BOX layer) of the silicon-on-insulator (SOI) semiconductor to enhance a performance index of an RF-SOI switch. The semiconductor device with voids within a silicon-on-insulator (SOI) structure includes a semiconductor substrate; an insulating layer disposed on the substrate; a silicon-on-insulator (SOI) layer disposed on the insulating layer; a device isolation layer and an active area disposed within the SOI layer; one or more voids disposed within the insulating layer; and a sealing insulating sealing an opening of the void.

Claims (17)

1. A semiconductor device with voids within a silicon-on-insulator (SOI) structure comprising:

a semiconductor substrate;

an insulating layer disposed on the substrate;

a silicon-on-insulator (SOI) layer disposed on the insulating layer;

a device isolation layer and an active area disposed within the SOI layer;

a void disposed within the insulating layer; and

a sealing insulating layer or film sealing an opening of the void.

2. The semiconductor device of claim 1 , further comprising another insulating layer disposed on a surface of the void.

3. The semiconductor device of claim 2 , wherein at least a part of a drain region, a source region, or a channel region of the active area is formed above an upper region of the void.

4. The semiconductor device of claim 1 , further comprising a void protection layer disposed along sidewalls of the void.

5. The semiconductor device of claim 1 , further comprising a protection layer disposed along sidewalls of the device isolation layer.

6. The semiconductor device of claim 1 , comprising a protection layer and another insulating layer disposed between the device isolation layer and the void.

7. The semiconductor device of claim 1 , wherein the semiconductor device comprises at least one of a CMOS(Complementary Metal-Oxide Semiconductor), an NMOS(N-type Metal-Oxide Semiconductor), a PMOS(P-type Metal-Oxide Semiconductor), an LDMOS(Laterally Diffused Metal-Oxide Semiconductor), a BJT(Bipolar Junction Transistor), a Diode, a Schottky diode, GaAs, InP, and GaN-based devices such as MESFETs, HEMTs, pHEMTs, MIS-HEMTs, or MOSFETs.

8. The semiconductor device of claim 1 , wherein the void is filled with pure nitrogen or under vacuum.

9. The semiconductor device of claim 1 , wherein a length of the void is longer than a length of the opening.

10. The semiconductor device of claim 1 , wherein the void has a horizontal type shape or alignment parallel to a top surface of the substrate.

11. The semiconductor device of claim 1 , wherein the void has a larger width in a horizontal direction than a vertical height of the insulating layer.

Assignments (3)
CHANGE OF NAME Recorded Mar 12, 2024
From: KEY FOUNDRY CO., LTD.
To: SK KEYFOUNDRY INC.
Reel/Frame 066794/0290 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2020
From: MAGNACHIP SEMICONDUCTOR, LTD.
To: KEY FOUNDRY CO., LTD.
Reel/Frame 053703/0227 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 3, 2015
From: HEBERT, FRANCOIS
To: MAGNACHIP SEMICONDUCTOR, LTD.
Reel/Frame 034876/0403 →