Method of forming a complementary metal oxide semiconductor structure with N-type and P-type field effect transistors having symmetric source/drain junctions and optional dual silicides
In a method of forming a semiconductor structure, different sections of a dielectric layer are etched at different stages during processing to form a first gate sidewall spacer for a first FET (e.g., a NFET) and a second gate sidewall spacer for a second FET (e.g., a PFET) such that the first and second gate sidewall spacers are symmetric. Raised source/drain regions for the first FET are formed immediately following first gate sidewall spacer formation and raised source/drain regions for the second FET are formed immediately following second gate sidewall spacer formation. Since the gate sidewall spacers of the two FETs are symmetric, the source/drain junctions of the two FETs will also be symmetric. Additionally, due to an etch stop layer formed on the raised source/drain regions of the first FET, but not the second FET, different metal silicides on the raised source/drain regions of the different FETs.
1. A method of forming a semiconductor structure comprising:
forming a first dielectric layer comprising a first section and a second section, said first section being over a first gate structure on a first semiconductor body of a first transistor and said second section being over a second gate structure on a second semiconductor body of a second transistor;
forming a mask on said second section of said first dielectric layer;
etching said first section of said first dielectric layer to form a first gate sidewall spacer on said first gate structure and to expose first source/drain regions of said first semiconductor body;
forming first raised source/drain regions on said first source/drain regions such that said first gate sidewall spacer is between said first raised source/drain regions and said first gate structure;
removing said mask;
forming a second dielectric layer on said first gate structure, said first gate sidewall spacer and said first semiconductor body, said second dielectric layer further extending over said second section of said first dielectric layer;
forming a third dielectric layer on said second dielectric layer;
forming an additional mask on said third dielectric layer above said first gate structure, said first gate sidewall spacer and said first raised source/drain regions;
etching said third dielectric layer and said second dielectric layer to expose said second section of said first dielectric layer;
etching said second section of said first dielectric layer to form a second gate sidewall spacer on said second gate structure and to expose second source/drain regions of said second semiconductor body; and,
forming second raised source/drain regions on said second source/drain regions such that said second gate sidewall spacer is between said second raised source/drain regions and said second gate structure.
2. The method of claim 1 , said first gate sidewall spacer and said second gate sidewall spacer having approximately equal thicknesses such that said first raised source/drain regions are separated from a first channel region in said first semiconductor body and said second raised source/drain regions are separated from a second channel region in said second semiconductor body by approximately equal distances.
3. The method of claim 1 ,
said forming of said first raised source/drain regions comprising epitaxially depositing a first epitaxial silicon layer on said first source/drain regions and, during said epitaxially depositing of said first epitaxial silicon layer, in situ doping said first epitaxial silicon layer with a first dopant, and
said forming of said second raised source/drain regions comprising epitaxially depositing a second epitaxial silicon layer on said second source/drain regions and, during said epitaxially depositing of said second epitaxial silicon layer, in situ doping said second epitaxial silicon layer with a second dopant that is different from said first dopant.
4. The method of claim 1 , said second dielectric layer comprising a different dielectric material than said first dielectric layer and said third dielectric layer.
5. The method of claim 1 , said first transistor comprising a N-type field effect transistor and said second transistor comprising a P-type field effect transistor.
6. A method of forming a semiconductor structure comprising:
forming a first dielectric layer comprising a first section and a second section, said first section being over a first gate structure on a first semiconductor body of a first transistor and said second section being over a second gate structure on a second semiconductor body of a second transistor;
forming a mask on said second section of said first dielectric layer;
etching said first section of said first dielectric layer to form a first gate sidewall spacer on said first gate structure and to expose first source/drain regions of said first semiconductor body;
forming first raised source/drain regions on said first source/drain regions such that said first gate sidewall spacer is between said first raised source/drain regions and said first gate structure;
removing said mask;
forming a second dielectric layer on said first gate structure, said first gate sidewall spacer and said first semiconductor body, said second dielectric layer further extending over said second section of said first dielectric layer;
forming a third dielectric layer on said second dielectric layer;
forming an additional mask on said third dielectric layer above said first gate structure, said first gate sidewall spacer and said first raised source/drain regions;
etching said third dielectric layer and said second dielectric layer to expose said second section of said first dielectric layer;
etching said second section of said first dielectric layer to form a second gate sidewall spacer on said second gate structure and to expose second source/drain regions of said second semiconductor body; and,
forming second raised source/drain regions on said second source/drain regions such that said second gate sidewall spacer is between said second raised source/drain regions and said second gate structure;
removing said additional mask;
forming a fourth dielectric layer on a remaining portion of said third dielectric layer above said first transistor, said fourth dielectric layer further extending over said second raised source/drain regions, said second gate sidewall spacer and said second gate structure;
forming multiple contact openings comprising:
first contact openings aligned above said first raised source/drain regions and extending to said second dielectric layer; and
second contact openings aligned above and extending to said second raised source/drain regions;
forming a conformal metal layer in said first contact openings and said second contact openings;
performing an anneal to form metal silicide layers on exposed surfaces of said second raised source/drain regions in said second contact openings; and,
after said metal silicide layers are formed, extending said first contact openings through said second dielectric layer to said first raised source/drain regions.
7. The method of claim 6 , further comprising: selectively removing said conformal metal layer and forming additional metal silicide layers different from said metal silicide layers on said first raised source/drain regions.
8. The method of claim 6 , further comprising:
selectively removing said conformal metal layer;
forming additional contact openings aligned above and extending to gate structures, said first contact openings being extended through said second dielectric layer to said first raised source/drain regions during said forming of said additional contact openings;
forming an additional conformal metal layer in said first contact openings, said second contact openings and said additional contact openings, said additional conformal metal layer creating additional metal silicide layers different from said metal silicide layers on said first raised source/drain regions; and
filling said first contact openings, said second contact openings and said additional contact openings with a fill metal.
9. The method of claim 6 , said first gate sidewall spacer and said second gate sidewall spacer having approximately equal thicknesses such that said first raised source/drain regions are separated from a first channel region of said first transistor and said second raised source/drain regions are separated from a second channel region of said second transistor by approximately equal distances.
10. The method of claim 6 ,
said forming of said first raised source/drain regions comprising epitaxially depositing a first epitaxial silicon layer on said first source/drain regions and, during said epitaxially depositing of said first epitaxial silicon layer, in situ doping said first epitaxial silicon layer with a first dopant, and
said forming of said second raised source/drain regions comprising epitaxially depositing a second epitaxial silicon layer on said second source/drain regions and, during said epitaxially depositing of said second epitaxial silicon layer, in situ doping said second epitaxial silicon layer with a second dopant that is different from said first dopant.
11. The method of claim 6 , said second dielectric layer comprising a different dielectric material than said first dielectric layer, said third dielectric layer and said fourth dielectric layer.