Three-dimensional devices having reduced contact length
Various embodiments comprise apparatuses and methods including a memory array having alternating levels of semiconductor materials and dielectric material with strings of memory cells formed on the alternating levels. One such apparatus includes a memory array formed starting adjacent to a surface of a substrate. Peripheral circuitry is formed on an elevated portion that is adjacent to the memory array and has an uppermost portion substantially coplanar with an uppermost surface of the memory array. Additional apparatuses and methods are described.
1. A method of forming a memory apparatus, the method comprising:
forming a memory array having a first surface proximate to a surface of a substrate and a second surface distal to the surface of the substrate, the memory array including:
forming a number of levels of semiconductor material and a number of levels of dielectric material, each of the levels of semiconductor material being separated from a respective adjacent one of the levels of semiconductor material by at least a respective one of the levels of dielectric material;
forming peripheral circuitry for the memory array, including:
forming an elevated portion adjacent to a peripheral edge of the substrate and adjacent to the memory array;
forming devices for interfacing with the memory array adjacent to a surface of the elevated portion that is more distal to the surface of the substrate than the first surface of the memory array; and
forming an upper surface of the peripheral circuitry to be substantially coplanar with an upper surface of the memory array to reduce an overall height of peripheral circuitry contacts to couple the peripheral circuitry contacts from the peripheral circuitry to respective ones of a plurality of interconnects; and
forming the plurality of interconnects between the memory array and the peripheral circuitry.
2. The method of claim 1 , further comprising forming the elevated portion from silicon.
3. The method of claim 1 , wherein forming the elevated portion comprises:
forming a dielectric material; and
forming a semiconductor material over at least an exposed uppermost portion of the dielectric material that is distal to the surface of the substrate.
4. A method of manufacturing a semiconductor apparatus, the method comprising:
forming a memory structure including semiconductor material levels and dielectric material levels alternately stacked proximate to a surface of a substrate in a memory array region;
forming a peripheral structure including peripheral circuits in a peripheral circuit region adjacent to the memory array region, the peripheral structure being elevated from the surface of the substrate, the forming of the peripheral structure including forming an upper surface of the peripheral structure to be substantially coplanar with an upper surface of the memory structure to reduce an overall height of peripheral circuitry contacts to couple the peripheral circuitry contacts from the peripheral structure to respective ones of a plurality of interconnects; and
forming the plurality of interconnects between the memory structure and the peripheral structure.
5. An apparatus, comprising:
a memory array having a number of levels of memory cells with each level being arranged substantially parallel to a surface of a substrate, the memory array having a first surface proximate to the surface of the substrate and a second surface distal from the surface of the substrate;
an elevated portion formed adjacent to a peripheral edge of the memory array, a surface of the elevated portion being substantially coplanar with the second surface of the memory array; and
peripheral circuitry formed adjacent to the surface of the elevated portion and configured to interface with the memory array, an upper surface of the peripheral circuitry being substantially coplanar with an upper surface of the memory array to reduce an overall height of peripheral circuitry contacts to couple the peripheral circuitry contacts from the peripheral circuitry to respective ones of a plurality of interconnects, the plurality of interconnects being formed between the memory array and the peripheral circuitry.
6. The apparatus of claim 5 , wherein the elevated portion is electrically coupled to the substrate.
7. An apparatus, comprising:
a memory array proximate to a surface of a substrate and having alternating levels of semiconductor materials and dielectric material with strings of memory cells formed along the alternating levels;
an elevated portion formed adjacent to the memory array, an upper surface of the elevated portion being distal from the surface of the substrate and substantially coplanar with an upper surface of the memory array; and
peripheral circuitry formed adjacent to the upper surface of the elevated portion, an upper surface of the peripheral circuitry being substantially coplanar with an upper surface of the memory array to reduce an overall height of peripheral circuitry contacts to couple the peripheral circuitry contacts from the peripheral circuitry to respective ones of a plurality of interconnects, the plurality of interconnects being formed between the memory array and the peripheral circuitry.
8. The apparatus of claim 7 , wherein the elevated portion comprises epitaxial silicon.
9. The apparatus of claim 7 , wherein the elevated portion comprises a dielectric material with a semiconductor material formed over at least an uppermost surface of the dielectric material.
10. An apparatus, comprising:
a memory array having a lower portion formed adjacent to a surface of a substrate, the memory array having alternating levels of semiconductor materials and dielectric materials extending away from the surface of the substrate, the alternating levels having strings of memory cells formed thereon;
an elevated portion formed on the surface of the substrate and located laterally adjacent to the memory array, the elevated portion having support circuitry located adjacent to an uppermost surface of the elevated portion, the support circuitry to supplement operations of the memory array; and
a pillar comprising a semiconductor material, the pillar extending from a lower portion of the memory array to an uppermost portion of the memory array that is distal from the surface of the substrate.
11. The apparatus of claim 10 , wherein the uppermost surface of the elevated portion is substantially coplanar with an uppermost portion of the memory array.
12. The apparatus of claim 10 , wherein the substrate comprises at least one material selected from materials consisting of elemental semiconductor wafers, compound semiconductor wafers, thin film head assemblies, and polyethylene-terephthalate (PET) films having a semiconductor layer formed thereon.
13. The apparatus of claim 10 , wherein the substrate comprises a region of a semiconductor material formed over a non-semiconductor material.
14. The apparatus of claim 13 , wherein the non-semiconductor material comprises at least one material selected from materials consisting of quartz and ceramic.
15. The apparatus of claim 10 , wherein the support circuitry comprises at least one of active devices to control operations of the memory array and passive components related to operations of the memory array.
16. The apparatus of claim 10 , wherein the elevated portion is substantially coplanar with an uppermost portion of the memory array to within 50% of an overall height of the pillar.
17. The apparatus of claim 10 , wherein the elevated portion is substantially coplanar with an uppermost portion of the memory array to within 10% of an overall height of the pillar.
18. The apparatus of claim 10 , wherein at least the uppermost surface of the elevated portion comprises at least one material selected from materials consisting of epitaxial silicon, a single-crystal semiconductor element, an amorphous semiconductor element, single-crystal semiconductor compound, and an amorphous semiconductor compound.
19. The apparatus of claim 18 , wherein the at least one material is formed over a dielectric material comprising the bulk of the elevated portion.
20. An apparatus, comprising:
a memory array having a lower portion formed adjacent to a surface of a substrate, the memory array having alternating levels of semiconductor materials and dielectric materials extending away from the surface of the substrate, the alternating levels having strings of memory cells formed thereon; and
an elevated portion formed on the surface of the substrate and located laterally adjacent to the memory array, the elevated portion having support circuitry located adjacent to an uppermost surface of the elevated portion, the support circuitry to supplement operations of the memory array, at least the uppermost surface of the elevated portion comprising at least one material selected from materials consisting of epitaxial silicon, a single-crystal semiconductor element, an amorphous semiconductor element, single-crystal semiconductor compound, and an amorphous semiconductor compound.