IP Library Granted Patent US 10,522,756
Granted Patent B2
US 10,522,756 · App. 14/615,963 · Granted Dec 31, 2019

Dual resistance heater for phase change memory devices

Inventors: Yudong Kim (Santa Clara, CA); Ilya V Karpov (Santa Clara, CA); Charles C. Kuo (Union City, CA); Maria Santina Marangon (Merate, IT); Tyler A. Lowrey (West Augusta, VA); Greg Atwood (Los Gatos, CA)
Assignee: Micron Technology, Inc.
H01L45/16H01L27/2427H01L45/06H01L45/126H01L45/1233H01L45/1286H01L45/141H01L45/1683
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Quick Facts
Patent No.
US 10,522,756
App. No.
14/615,963
Granted
Dec 31, 2019
Kind
B2
Abstract

In various examples, a dual resistance heater for a phase change material region is fabricated by forming a resistive material. Prior to forming the phase change material region over the resistive material, at least an upper portion of the resistive material is exposed to an implantation or plasma that increases the resistance of an upper portion of the resistive material relative to the remainder, or bulk, of the resistive material. As a result, the portion of the resistive material proximate to the phase change material region forms a heater because of its high resistance value, but the bulk of the resistive material has a relatively lower resistance value and, thus, does not increase the voltage drop and current usage of the device. Other methods and devices are disclosed.

Claims (15)

1. A method of fabricating a memory device, the method comprising:

forming a dielectric layer over a conductive material;

forming a first opening in the dielectric layer;

forming a dielectric spacer within the first opening in the dielectric layer, the spacer defining a second opening;

forming at least one resistive heater material within the second opening in the dielectric spacer;

wherein a top surface region of the at least one resistive heater material is recessed below the uppermost portion of the dielectric layer;

implanting ions into the recessed top surface region of the at least one resistive heater material, resulting in two regions of the resistive heater material, a top surface region and a bulk region, the top surface region having a higher resistance than the bulk region; and

forming a phase change material comprising a chalcogenide alloy, the phase change material programmable between different phase states having different resistances, the phase change material overlying and electrically coupled to the recessed top surface region of the at least one resistive heater material, the phase change material layer extending within the second opening to contact the recessed top surface region of the at least one resistive heater material, the phase change material filling the second opening to at least the height of the uppermost portion of the dielectric layer, the phase change material having a smaller lateral dimension adjacent the top surface region than at the height of the uppermost portion of the dielectric layer.

2. The method of claim 1 , wherein implanting ions into the top surface region increases the resistance value of the top surface region.

3. The method of claim 2 , wherein the implanted ions comprise silicon.

4. The method of claim 1 , wherein implanting ions into the recessed top surface region comprises exposing at least the top surface region to a plasma treatment.

5. The method of claim 4 , further comprising diffusing oxygen atoms into the top surface region through the plasma treatment.

6. The method of claim 1 , further comprising forming the top surface region of the at least one resistive heater material to have a smaller volume than the bulk region of the at least one resistive heater material.

7. The method of claim 1 , further comprising forming the first opening in the dielectric layer to be open to the conductive material; and forming the second opening in the dielectric spacer to be open to the conductive material.

8. The method of claim 1 , wherein the heater material comprises titanium nitride; and wherein the top surface region comprises titanium silicon nitride.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
Priority Claims (1)
EP 04107070 · Dec 30, 2004 · regional
Continuity (4)
Continuation 13970207 · Aug 19, 2013
Continuation 12980141 · Dec 28, 2010
Division 11312231 · Dec 19, 2005
Related Publication 20150188050A1 · Jul 2, 2015