IP Library Granted Patent US 9,589,916
Granted Patent B2
US 9,589,916 · App. 14/618,305 · Granted Mar 7, 2017

Inductively coupled transformer with tunable impedance match network

Inventors: Marvin Marbell (Morgan Hill, CA); E J Hashimoto (San Jose, CA); Bill Agar (Morgan Hill, CA)
Assignee: Infineon Technologies AG
H01L23/66H03F1/565H03F3/193H03H7/38H03F2200/534
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Quick Facts
Patent No.
US 9,589,916
App. No.
14/618,305
Granted
Mar 7, 2017
Kind
B2
Abstract

A packaged RF power transistor includes an RF input lead, a DC gate bias lead, an RF power transistor comprising gate, source and drain terminals, and an input match network. The input match network includes a primary inductor electrically connected to the RF input lead, a secondary inductor electrically connected to the gate terminal and to the DC gate bias lead, and a tuning capacitor electrically connected to the RF input lead and physically disconnected from the gate terminal. The input match network is configured to block DC voltages between the RF input lead and the gate terminal and to propagate AC voltages in a defined frequency range from the RF input lead to the gate terminal. The tuning capacitor is configured to adjust a capacitance of the input match network based upon a variation in DC voltage applied to the RF input lead.

Claims (52)

1. A packaged RF power transistor, comprising:

an RF input lead;

a DC gate bias lead;

an RF power transistor comprising gate, source and drain terminals; and

an input match network, comprising:

a primary inductor electrically connected to the RF input lead;

a secondary inductor electrically connected to the gate terminal and to the DC gate bias lead;

a tuning capacitor electrically connected to the RF input lead and physically disconnected from the gate terminal;

first and second segmented capacitor arrays arranged between the RF input lead and the RF power transistor;

a first set of bond wires electrically connected to the RF input lead and to the first and second segmented capacitor arrays; and

a second set of bond wires electrically connected to the gate terminal and to the first and second segmented capacitor arrays;

wherein the input match network is configured to block DC voltages between the RF input lead and the gate terminal and to propagate AC voltages in a defined frequency range from the RF input lead to the gate terminal,

wherein the tuning capacitor is configured to adjust a capacitance of the input match network based upon a variation in DC voltage applied to the RF input lead,

wherein the primary inductor is formed by sections of the first set of bond wires extending between the first and second segmented capacitor arrays, and

wherein the secondary inductor is formed by sections of the second set of bond wires extending between the first and second segmented capacitor arrays.

2. The packaged RF power transistor of claim 1 , wherein the primary and secondary inductors are inductively coupled to one another in a transformer configuration, the transformer being configured to block the DC voltages and to propagate the AC voltages, and wherein the tuning capacitor is electrically connected to the primary inductor.

3. The packaged RF power transistor of claim 1 , wherein the first segmented capacitor array comprises a plurality of variable capacitors alternating with a plurality of static capacitors, wherein the first set of bond wires is electrically connected to the variable capacitors in the first segmented capacitor array, wherein the second set of bond wires is electrically connected to the static capacitors in the first segmented capacitor array, and wherein the tuning capacitor is formed from the variable capacitors in the first segmented capacitor array.

4. The packaged RF power transistor of claim 3 , wherein the second segmented capacitor array comprises a plurality of variable capacitors alternating with a plurality of static capacitors, wherein the first set of bond wires is electrically connected to the variable capacitors in the second segmented capacitor array, wherein the second set of bond wires is electrically connected to the static capacitors in the second segmented capacitor array, and further comprising a second tuning capacitor that is formed from the variable capacitors in the first and second segmented capacitor arrays.

5. The packaged RF power transistor of claim 1 , wherein the input match network further comprises a third capacitor block arranged between the RF input lead and the RF power transistor and comprising a variable capacitor, wherein the first set of bond wires is electrically connected to the third capacitor block, and wherein the tuning capacitor comprises the variable capacitor of the third capacitor block.

6. The packaged RF power transistor of claim 5 , wherein each of the capacitors in the first and second segmented arrays of capacitors are static capacitors.

7. A packaged RF power transistor of claim 1 , wherein the tuning capacitor is configured to operate at a DC bias of between 0 and 40 volts, and wherein the RF power transistor is configured to operate at a DC bias of between 0 and 4 volts.

8. A packaged RF power transistor, comprising:

an RF input lead;

a DC gate bias lead;

an RF power transistor comprising gate, source and drain terminals; and

an input match network, comprising:

a primary inductor electrically connected to the RF input lead;

a secondary inductor electrically connected to the gate terminal and to the DC gate bias lead; and

a tuning capacitor electrically connected to the RF input lead and physically disconnected from the gate terminal;

first and second segmented capacitor arrays arranged between the RF input lead and the RF power transistor;

a first set of bond wires electrically connected to the RF input lead and to the first and second segmented capacitor arrays; and

a second set of bond wires electrically connected to the gate terminal and to the first and second segmented capacitor arrays;

wherein nominal component values of the RF power transistor and the input match network are optimized such that a maximum gain is realized at a center frequency of the defined frequency range,

wherein actual component values of the RF power transistor and the input match network deviate from the nominal component values by a percentage,

wherein a capacitance value of the tuning capacitor is adjustable based upon a variation in DC voltage applied to the RF input lead so as to compensate for the deviation between the nominal component values and the actual component values,

wherein the primary inductor is formed by sections of the first set of bond wires extending between the first and second segmented capacitor arrays, and

wherein the secondary inductor is formed by sections of the second set of bond wires extending between the first and second segmented capacitor arrays.

9. The packaged RF power transistor of claim 8 , wherein the nominal component values of the RF power transistor and the input match network comprise at least one of: input capacitance of the RF power transistor, output capacitance of the RF power transistor, a capacitance of static capacitors in the input match network, and an inductance of bond wires in the input match network, and wherein the actual component values deviate from the nominal component values by +/−5 percent.

10. The packaged RF power transistor of claim 9 , wherein the actual input capacitance of the RF power transistor is 5 percent higher than the nominal component value, wherein the inductance of one of the bond wires in the input match network is 5 percent higher than the nominal component value, wherein the deviation of the actual component values from the nominal component values shifts an insertion phase of the packaged RF power transistor by 11 percent, and wherein a capacitance value of the tuning capacitor is adjustable to completely compensate for the shift in the insertion phase.

11. A method of packaging an RF power transistor, the method comprising:

providing a packaged RF power transistor, comprising an RF input lead, a DC gate bias lead, an RF power transistor comprising gate, source and drain terminals, and an input match network, comprising:

a transformer coupled between the RF input lead and the gate terminal configured to block DC voltages between the RF input lead and the gate terminal and to propagate AC voltages in a defined frequency range from the RF input lead to the gate terminal;

a tuning capacitor electrically connected to the RE Input lead and physically disconnected from the gate terminal;

first and second segmented capacitor arrays arranged between the RF input lead and the RF power transistor;

a first set of bond wires electrically connected to the RF input lead and to the first and second segmented capacitor arrays; and

a second set of bond wires electrically connected to the gate terminal and to the first and second segmented capacitor arrays,

testing the packaged RF power transistor for a deviation between nominal component values of the RF power transistor and the input match network and actual component values of the RF power transistor and the input match network; and

determining a DC bias to be applied to the tuning capacitor via the RF input lead that compensates for the deviation between nominal component values and actual component values,

wherein the primary inductor is formed by sections of the first set of bond wires extending between the first and second segmented capacitor arrays, and

wherein the secondary inductor is formed by sections of the second set of bond wires extending between the first and second segmented capacitor arrays.

12. The method of claim 11 , wherein testing the packaged RF power transistor comprises measuring at least one of: an input capacitance of the RF power transistor, an output capacitance of the RF power transistor, a capacitance at least one of the static capacitors in the input match network, and an inductance of at least one of the bond wires in the input match network.

13. The method of claim 11 , wherein testing the packaged RF power transistor comprises measuring an insertion phase of the packaged RF power transistor, and wherein determining the DC bias comprises determining a capacitance value of the tuning capacitor that will shift the insertion phase closer to a nominal insertion phase.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 29, 2023
From: WOLFSPEED, INC.
To: MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC.
Reel/Frame 066236/0086 →
CHANGE OF NAME Recorded Jan 19, 2022
From: CREE, INC.
To: WOLFSPEED, INC.
Reel/Frame 058774/0432 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 22, 2018
From: INFINEON TECHNOLOGIES AG
To: CREE, INC.
Reel/Frame 045870/0504 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 20, 2015
From: AGAR, BILL; HASHIMOTO, EJ; MARBELL, MARVIN
To: INFINEON TECHNOLOGIES AG
Reel/Frame 034994/0666 →
Continuity (1)
Related Publication 20160233849A1 · Aug 11, 2016