Semiconductor packaging structure having stacked seed layers
A semiconductor packaging structure includes a chip, a metal barrier layer, a dielectric layer and two metal seed layers. The chip has a top surface, connection pads on the top surface, and a passivation layer on the top surface and partly covering the connection pads. The metal barrier layer is disposed on each of the connection pads; the dielectric layer is disposed on the passivation layer and the metal barrier layer, and has through holes to expose the metal barrier layer. The first of the metal seed layers is disposed on the dielectric layer and the exposed metal barrier layer, while the second metal seed layer is disposed on the first metal seed layer. Therefore, the metal barrier layer can effectively prevent damage to the connection pads of the chip during the manufacturing process.
1. A semiconductor packaging structure, comprising:
a chip, having a top surface, a plurality of connection pads and a passivation layer, wherein the connection pads and the passivation layer are disposed on the top surface, and the passivation layer partly covers the connection pads;
a metal barrier layer, disposed on each of the connection pads;
a first dielectric layer, disposed on the passivation layer and the metal barrier layer, and having a plurality of through holes to expose the metal barrier layer from the first dielectric layer;
a first metal seed layer, disposed on the first dielectric layer and the exposed metal barrier layer; and
a second metal seed layer, disposed on the first metal seed layer.
2. The semiconductor packaging structure of claim 1 , wherein materials to manufacture the metal barrier layer and the first metal seed layer are the same.
3. The semiconductor packaging structure of claim 2 , wherein the materials include nickel or titanium.
4. The semiconductor packaging structure of claim 1 , wherein materials to manufacture the second metal seed layer include gold or copper.
5. The semiconductor packaging structure of claim 1 , wherein the first metal seed layer is disposed on part of the first dielectric layer, and the semiconductor packaging structure further comprises a redistribution layer disposed on the second metal seed layer.
6. The semiconductor packaging structure of claim 5 , wherein materials to manufacture the redistribution layer and the second metal seed layer are the same.
7. The semiconductor packaging structure of claim 6 , wherein the materials include copper.
8. The semiconductor packaging structure of claim 5 , further comprising:
a third dielectric layer, disposed on the redistribution layer and having a plurality of through holes to expose part of the redistribution layer from the third dielectric layer; and
a plurality of bumps, disposed on the exposed redistribution layer.
9. The semiconductor packaging structure of claim 8 , further comprising an alloy layer disposed between the exposed redistribution layer and the bumps.