Semiconductor device with device separation structures
A semiconductor device includes a first gate electrode structure, a second gate electrode structure, a device separation structure, and cell separation structures. The first gate electrode structure is buried in a semiconductor portion in a first cell array at a distance to a first surface of the semiconductor portion. The first gate electrode structure includes parallel array stripes. The second gate electrode structure is buried in the semiconductor portion in a second cell array adjacent to the first cell array. The second gate electrode structure includes parallel array stripes. The device separation structure is between the first and second cell arrays. The device separation structure has a first width. The cell separation structures have at most a second width smaller than the first width and notching, at the first surface, semiconductor fins formed from sections of the semiconductor portion between the array trenches.
1. A semiconductor device, comprising:
a first gate electrode structure buried in a semiconductor portion in a first cell array at a distance to a first surface of the semiconductor portion, the first gate electrode structure including parallel array stripes;
a second gate electrode structure buried in the semiconductor portion in a second cell array adjacent to the first cell array, the second gate electrode structure including parallel array stripes;
a device separation structure between the first and second cell arrays, the device separation structure having a first width; and
cell separation structures having at most a second width smaller than the first width and notching, at the first surface, semiconductor fins formed from sections of the semiconductor portion between the array trenches.
2. The semiconductor device according to claim 1 , wherein the device separation structure includes a first section oriented to the first surface and an extension section oriented to a second surface of the semiconductor portion parallel to the first surface, the extension section having a smaller lateral cross-sectional area parallel to the first surface than the extension section.
3. The semiconductor device according to claim 1 , wherein the device separation structure includes a first section oriented to the first surface and an extension section oriented to a second surface of the semiconductor portion parallel to the first surface, the extension section having a greater lateral cross-sectional area parallel to the first surface than the extension section.
4. The semiconductor device according to claim 1 ,
wherein the device separation structure includes an insulator layer in a first section oriented to the first surface, the insulator layer extending parallel to a vertical interface with a semiconductor material of the semiconductor portion, and
wherein the insulator layer and the cell separation structures are made of a same material.
5. The semiconductor device according to claim 1 , wherein the device separation structure includes a void.
6. The semiconductor device according to claim 1 , wherein a buried edge of the device separation structure has a greater distance to the first surface than a buried edge of the gate electrode structures.
7. The semiconductor device according to claim 1 , wherein ridges formed from portions of the semiconductor portion separate the device separation structure from the first and second cell arrays.
8. The semiconductor device according to claim 1 , wherein the device separation structure completely surrounds the first cell array in lateral directions parallel to the first surface.
9. An active drift zone field effect transistor (ADZFET), comprising:
a first gate electrode structure buried in a semiconductor portion in a first cell array at a distance to a first surface of the semiconductor portion, the first gate electrode structure including parallel array stripes;
a second gate electrode structure buried in the semiconductor portion in a second cell array adjacent to the first cell array, the second gate electrode structure including parallel array stripes;
a device separation structure between the first and second cell arrays, the device separation structure having a first width; and
cell separation structures having at most a second width smaller than the first width and notching, at the first surface, semiconductor fins formed from sections of the semiconductor portion between the array trenches.