IP Library Granted Patent US 9,431,311
Granted Patent B1
US 9,431,311 · App. 14/626,758 · Granted Aug 30, 2016

Semiconductor package with elastic coupler and related methods

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Quick Facts
Patent No.
US 9,431,311
App. No.
14/626,758
Granted
Aug 30, 2016
Kind
B1
Abstract

A semiconductor package includes: a die coupled to a substrate; a housing coupled to the substrate and at least partially enclosing the die within a cavity of the housing, and; a pin fixedly coupled to the housing and electrically coupled with the die. The pin includes a reversibly elastically deformable lower portion, which in implementations includes a spring, configured to compress to prevent a lower end of the pin from lowering beyond a predetermined point relative to the substrate when the housing is lowered to be coupled to the substrate. The pin is fixedly coupled in a top of the housing and is configured to be coupled with the substrate by lowering the housing towards the substrate. In implementations the pin includes two rigid portions coupled together only with a coil spring, the spring biasing the rigid portions away from one another when the housing is lowered towards the substrate.

Claims (11)

1. A method of forming a semiconductor package, comprising:

securing a pin to a housing, the pin comprising a spring located in the pin between the housing and a substrate;

lowering the housing relative to the substrate having a semiconductor die (die) coupled thereon to at least partially enclose the die within a cavity of the housing,

wherein the lower end of the pin comprises a flat plate and wherein, prior to lowering the housing, the flat plate is coupled to the upper portion of the pin through only the spring; and

while lowering the housing, compressing the spring so that a lower end of the pin does not lower beyond a predetermined point relative to the flat plate and the lower end of the pin so that an upper portion of the pin is biased towards the housing,

wherein lowering the housing comprises electrically coupling the pin with the die.

2. The method of claim 1 , further comprising securing the housing to the substrate.

3. The method of claim 2 , wherein securing the housing to the substrate comprises maintaining compression of the spring.

4. The method of claim 1 , wherein compressing the spring comprises compressing the spring between two rigid portions of the pin.

5. The method of claim 4 , wherein compressing the spring comprises biasing the two rigid portions of the pin away from one another.

6. The method of claim 1 , wherein compressing the spring comprises compressing the spring along a direction substantially parallel with a longest length of the pin.

Assignments (4)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 19, 2015
From: LIN, YUSHENG; CARNEY, FRANCIS J.; CHEW, CHEE HIONG
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 034989/0130 →