IP Library Granted Patent US 9,704,769
Granted Patent B2
US 9,704,769 · App. 14/627,347 · Granted Jul 11, 2017

Semiconductor device and method of forming encapsulated wafer level chip scale package (EWLCSP)

Inventors: Thomas J. Strothmann (Tuscon, AZ); Seung Wook Yoon (Singapore, SG); Yaojian Lin (Singapore, SG)
Assignee: STATS ChipPAC Pte. Ltd.
H01L23/3114H01L23/3157H01L24/96H01L24/97H01L21/561H01L21/568H01L23/562H01L2224/04105H01L2224/11H01L2224/12105H01L2224/73267H01L2924/18162H01L2924/3511
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,704,769
App. No.
14/627,347
Granted
Jul 11, 2017
Kind
B2
Abstract

A semiconductor device has a semiconductor die and an encapsulant around the semiconductor die. A fan-in interconnect structure is formed over the semiconductor die while leaving the encapsulant devoid of the interconnect structure. The fan-in interconnect structure includes an insulating layer and a conductive layer formed over the semiconductor die. The conductive layer remains within a footprint of the semiconductor die. A portion of encapsulant is removed from over the semiconductor die. A backside protection layer is formed over a non-active surface of the semiconductor die after depositing the encapsulant. The backside protection layer is formed by screen printing or lamination. The backside protection layer includes an opaque, transparent, or translucent material. The backside protection layer is marked for alignment using a laser. A reconstituted panel including the semiconductor die is singulated through the encapsulant to leave encapsulant disposed over a sidewall of the semiconductor die.

Claims (52)

1. A method of making a semiconductor device, comprising:

providing a plurality of semiconductor die;

depositing an encapsulant around and over the semiconductor die;

forming a first insulating layer over an active surface of the semiconductor die and in contact with the encapsulant;

forming an interconnect structure over the first insulating layer and semiconductor die by,

(a) forming a conductive layer, and

(b) forming a bump over the conductive layer, wherein the entire interconnect structure is disposed within a footprint of the semiconductor die as a fan-in interconnect structure;

forming a protection layer over a top surface of the encapsulant and over a second surface of the semiconductor die opposite the active surface; and

singulating the plurality of semiconductor die through the protective layer, encapsulant, and first insulating layer to leave a thickness of the encapsulant disposed over a side surface of the semiconductor die less than 100 micrometers and the first insulating layer and protection layer terminating at an outside surface of the encapsulant.

2. The method of claim 1 , further including removing a portion of the encapsulant to leave the top surface of the encapsulant coplanar with the second surface of the semiconductor die.

3. The method of claim 1 , further including forming a second insulating layer over the conductive layer, wherein the second insulating layer terminates at the outside surface of the encapsulant.

4. The method of claim 1 , wherein the protective material includes a transparent material or translucent material.

5. The method of claim 1 , wherein the protective material includes an opaque material.

6. The method of claim 1 , wherein the thickness of the encapsulant disposed over the side surface of the semiconductor die ranges from 30 to 50 micrometers.

7. A method of making a semiconductor device, comprising:

providing a semiconductor die;

depositing an encapsulant around and over the semiconductor die;

forming a first insulating layer over the encapsulant and a first surface of the semiconductor die;

forming an interconnect structure over the first insulating layer and semiconductor die by,

(a) forming a conductive layer, and

(b) forming a bump over the conductive layer, wherein the entire interconnect structure is disposed within a footprint of the semiconductor die; and

forming a protection layer over a top surface of the encapsulant and over a second surface of the semiconductor die opposite the first surface of the semiconductor die, wherein a thickness of the encapsulant disposed over a side surface of the semiconductor die is less than 100 micrometers and the first insulating layer and protection layer terminate at an outside surface of the encapsulant.

8. The method of claim 7 , further including removing a portion of the encapsulant to leave the top surface of the encapsulant coplanar with the second surface of the semiconductor die.

9. The method of claim 7 , further including forming a second insulating layer over the conductive layer, wherein the second insulating layer terminates at the outside surface of the encapsulant.

10. The method of claim 7 , wherein the protective material includes a transparent material or translucent material.

11. The method of claim 7 , wherein the protective material includes an opaque material.

12. The method of claim 7 , wherein the thickness of the encapsulant disposed over the side surface of the semiconductor die ranges from 30 to 50 micrometers.

13. A method of making a semiconductor device, comprising:

providing a semiconductor die;

depositing an encapsulant around and over the semiconductor die;

forming a first insulating layer over the encapsulant and a first surface of the semiconductor die;

forming an interconnect structure over the first insulating layer and semiconductor die by,

(a) forming a conductive layer, and

(b) forming a bump over the conductive layer, wherein the interconnect structure is disposed within a footprint of the semiconductor die; and

forming a protection layer over a surface of the encapsulant and over a second surface of the semiconductor die opposite the first surface of the semiconductor die, wherein a thickness of the encapsulant disposed over a side surface of the semiconductor die is less than 100 micrometers.

14. The method of claim 13 , further including removing a portion of the encapsulant to leave the surface of the encapsulant coplanar with the second surface of the semiconductor die.

15. The method of claim 13 , wherein the first insulating layer and protection layer terminate at an outside surface of the encapsulant.

16. The method of claim 13 , further including forming a second insulating layer over the conductive layer, wherein the second insulating layer terminates at an outside surface of the encapsulant.

17. The method of claim 13 , wherein the protective material includes a transparent material or translucent material.

18. The method of claim 13 , wherein the protective material includes an opaque material.

19. The method of claim 13 , wherein the thickness of the encapsulant disposed over the side surface of the semiconductor die ranges from 30 to 50 micrometers.

20. A method of making a semiconductor device, comprising:

providing a semiconductor die;

depositing an encapsulant around and over the semiconductor die;

forming a first insulating layer over the encapsulant and a first surface of the semiconductor die; and

forming an interconnect structure over the first insulating layer and semiconductor die by,

(a) forming a conductive layer, and

(b) forming a bump over the conductive layer, wherein the interconnect structure is disposed within a footprint of the semiconductor die;

wherein a thickness of the encapsulant disposed over a side surface of the semiconductor die is less than 100 micrometers.

21. The method of claim 20 , wherein the first insulating layer terminates at an outside surface of the encapsulant.

22. The method of claim 20 , wherein a thickness of the encapsulant over the semiconductor die is at least 100 micrometers.

23. The method of claim 20 , wherein the thickness of the encapsulant disposed over the side surface of the semiconductor die ranges from 30 to 50 micrometers.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 18, 2019
From: STATS CHIPPAC PTE. LTD.
To: JCET SEMICONDUCTOR (SHAOXING) CO., LTD.
Reel/Frame 051365/0680 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 17, 2015
From: STROTHMANN, THOMAS J.; YOON, SEUNG WOOK; LIN, YAOJIAN
To: STATS CHIPPAC, LTD.
Reel/Frame 035186/0213 →
Continuity (2)
Provisional Application 61945739 · Feb 27, 2014
Related Publication 20150243575A1 · Aug 27, 2015