Floating staircase word lines and process in a 3D non-volatile memory having vertical bit lines
A 3D nonvolatile memory has memory elements arranged in a three-dimensional pattern with a plurality of memory layers stacked over a semiconductor substrate. It has a 2D array of vertical bit lines and a plurality of staircase word lines. Each staircase word line has a series of alternating segments and risers and traverses the plurality of memory layers with a segment in each memory layer. The plurality of staircase word lines have their segments lined up to form a 2D array of stacks of segments. Riser for a pair of segments from each adjacent stacks at different memory layers is provided by a conductive sidewall layer of a stairwell disposed between the adjacent stacks. Multiple insulated conductive sidewall layers provide multiple risers for the adjacent stacks. Layer-by-layer stairwell excavation and sidewall processes between adjacent stacks create risers for different pairs of segments between stacks to form the staircase word lines.
1. A non-volatile memory, comprising:
memory elements arranged in a three-dimensional pattern in a plurality of memory layers stacked over a semiconductor substrate;
a plurality of segments disposed to form a plurality of arrays of segments, each array of segments disposed in a respective memory layer of the plurality of memory layers, each segment of the plurality of segments being a segment of a respective staircase word line, the respective staircase word line extending from a bottom memory layer to a top memory layer of the plurality of memory layers,
wherein the plurality of segments are further disposed to form an array of stacks of segments, each stack of segments comprising a column of segments that spans the plurality of memory layers; and
a stairwell located between adjacent first and second stacks of segments, said stairwell having a sidewall comprising an insulated conductive sidewall layer, the insulated conductive sidewall layer providing a riser to connect a first segment in the first stack to a second segment in the second stack, and wherein the first and second segments are disposed in different memory layers of the plurality of memory layers.
2. The non-volatile memory of claim 1 , wherein the first segment is disposed in a first a memory layer and the second segment is disposed in a second memory layer directly above the first memory layer.
3. The non-volatile memory of claim 1 , further comprising:
a plurality of bit line pillars disposed through the plurality of memory layers, wherein each segment of the plurality of segments crosses a predetermined number of bit line pillars of the plurality of bit line pillars.
4. The non-volatile memory of claim 1 , further comprising:
a word line driver disposed above the top memory layer of the plurality of memory layers, the word line driver connected to the respective staircase word line.
5. The non-volatile memory of claim 1 , wherein the plurality of segments are metallic.
6. The non-volatile memory of claim 1 , wherein the insulated conducting conductive sidewall layer is metallic.
7. The non-volatile memory of claim 1 , wherein the insulated conductive sidewall layer comprises interleaving insulating oxide layers.
8. The non-volatile memory of claim 1 , wherein the stairwell comprises an oxide filling material.
9. The non-volatile memory of claim 1 , wherein a resistance of a memory element of the memory elements varies inversely proportionally to a voltage or a current applied to the memory element.
10. A non-volatile memory, comprising:
a plurality of segments disposed in a plurality of layers to form first and second segment stacks, each of the first and second segment stacks spanning the plurality of layers, and each segment of the plurality of segments corresponding to a segment of a respective staircase word line; and
a stairwell, located between the first and second segment stacks, comprising an insulated conductive sidewall layer, the insulated conductive sidewall layer comprising a riser to connect a first segment of the first segment stack to a second segment of the second segment stack, the first and second segments being disposed in different layers of the plurality of layers.
11. The non-volatile memory of claim 10 , wherein the first segment is disposed in a first a layer and the second segment is disposed in a second layer directly above the first layer.
12. The non-volatile memory of claim 10 , further comprising:
a plurality of memory elements disposed in the plurality of layers to form a three-dimensional arrangement.
13. The non-volatile memory of claim 10 , wherein the respective staircase word line extends from a bottom layer to a top layer of the plurality of layers.
14. The non-volatile memory of claim 10 , further comprising:
a word line driver disposed above a top layer of the plurality of layers, the word line driver connected to the respective staircase word line.
15. The non-volatile memory of claim 10 , wherein the plurality of segments are metallic.
16. The non-volatile memory of claim 10 , wherein the insulated conductive sidewall layer is metallic.
17. The non-volatile memory of claim 10 , wherein the insulated conductive sidewall layer comprises interleaving insulating oxide layers.
18. A non-volatile memory, comprising:
first and second segment stacks, each of the first and second segment stacks comprising a respective plurality of segments, each segment of the respective plurality of segments disposed in a respective layer of a plurality of layers and corresponding to a segment of a respective staircase word line; and
a stairwell, located between the first and second segment stacks, comprising a conductive sidewall layer, the conductive sidewall layer comprising a riser to connect a first segment of the first segment stack to a second segment of the second segment stack, the first and second segments being disposed in different layers of the plurality of layers.
19. The non-volatile memory of claim 18 , wherein the conductive sidewall layer is insulated by interleaving oxide layers.
20. The non-volatile memory of claim 18 , wherein the first segment is disposed in a first a layer and the second segment is disposed in a second layer directly above the first layer.