IP Library Granted Patent US 9,641,776
Granted Patent B2
US 9,641,776 · App. 14/633,261 · Granted May 2, 2017

Image sensor with flexible interconnect capabilities

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Quick Facts
Patent No.
US 9,641,776
App. No.
14/633,261
Granted
May 2, 2017
Kind
B2
Abstract

Electronic devices may include image sensors having configurable image sensor pixel interconnections. Image sensors may include image sensor pixels coupled to analog circuitry via configurable interconnect circuitry. The analog circuitry may include many analog circuit blocks. The analog circuit blocks may control and read out signals from associated image sensor pixels. The configurable interconnect circuitry may be controlled to reroute the connections between the analog circuit blocks and specific groups of image sensor pixels. Digital circuitry may be coupled to the analog circuitry via configurable interconnect circuitry. The digital circuitry may include digital circuit blocks. There may be significantly more image pixels controlled by a small number of analog circuit blocks, which are in turn controlled by a smaller number of digital circuit blocks. The image sensor pixel array, the configurable interconnect circuitry, the analog circuitry, and the digital circuitry may be vertically stacked.

Claims (29)

1. A method of operating an image sensor, comprising:

sensing light with an array of image sensor pixels arranged in rows and columns, wherein the array of image sensor pixels is organized into respective groups of image sensor pixels and wherein each of the respective groups of image sensor pixels includes image sensor pixels from at least two rows and at least two columns; and

simultaneously accessing each image sensor pixel in a selected one of the respective groups of image sensor pixels, wherein the image sensor further includes a plurality of control circuits each of which is operable to access each image sensor pixel in the array, and wherein simultaneously accessing each image sensor pixel in the selected one of the respective groups comprises:

selectively routing control signals from a first control circuit in the plurality of control circuits to at least a first portion of image sensor pixels in selected group; and

selectively routing pixel output signals from the first portion of image sensor pixels to the first control circuit.

2. The method defined in claim 1 , wherein simultaneously accessing each image sensor pixel in the selected one of the respective groups of image sensor pixels comprises simultaneously accessing image sensor pixels from at least two adjacent rows.

3. The method defined in claim 2 , wherein simultaneously accessing each image sensor pixel in the selected one of the respective groups of image sensor pixels comprises simultaneously accessing image sensor pixels from at least two adjacent columns.

4. The method defined in claim 1 , wherein the respective groups of image sensor pixels includes a first group of image sensor pixels and a second group of image sensor pixels that is different than the first group, the method further comprising:

simultaneously accessing each image sensor pixel in the first group during a first time period; and

simultaneously accessing each image sensor pixel in the second group during a second time period that is different than the first time period.

5. The method defined in claim 1 , further comprising:

with configurable interconnect circuitry, routing the control signals and the pixel output signals between the plurality of control circuits and the image sensor pixels in the selected group.

6. The method defined in claim 1 , wherein simultaneously accessing each image sensor pixel in the selected group of image sensor pixels comprises simultaneously accessing each image sensor pixel in the selected group of image sensor pixels without accessing at least some image sensor pixels in the at least two rows that are part of another group of image sensor pixels that is different than the selected group.

7. A method of operating an image sensor, comprising:

sensing light with an array of image sensor pixels arranged in rows and columns, wherein the array of image sensor pixels is organized into respective groups of image sensor pixels, wherein each of the respective groups of image sensor pixels includes image sensor pixels from at least two rows and at least two columns; and

simultaneously accessing each image sensor pixel in a selected one of the respective groups of image sensor pixels, wherein the image sensor further includes a plurality of control circuits each of which is operable to access each image sensor pixel in the array, and wherein simultaneously accessing each image sensor pixel in the selected one of the respective groups further comprises:

selectively routing control signals from a first control circuit in the plurality of control circuits to at least a first portion of image sensor pixels in selected group;

selectively routing pixel output signals from the first portion of image sensor pixels to the first control circuit;

selectively routing control signals from a second control circuit in the plurality of control circuits to at least a second portion of image sensor pixels in the selected group that is different than the first portion; and

selectively routing pixel output signals from the second portion of image sensor pixels to the second control circuit.

8. A method of operating an image sensor, comprising:

sensing light with an array of image sensor pixels arranged in rows and columns, wherein the array of image sensor pixels is organized into respective groups of image sensor pixels, wherein each of the respective groups of image sensor pixels includes image sensor pixels from at least two rows and at least two columns; and

simultaneously accessing each image sensor pixel in a selected one of the respective groups of image sensor pixels, wherein the image sensor further includes a plurality of analog circuit blocks each of which is operable to access each image sensor pixel in the array, wherein each analog circuit block is configured to supply pixel control signals to configurable interconnect circuitry, and wherein each analog circuit block is configured to receive pixel output signals from the configurable interconnect circuitry.

9. The method defined in claim 8 , wherein simultaneously accessing each image sensor pixel in the selected one of the respective groups comprises:

with the configurable interconnect circuitry, selectively routing the pixel control signals from a first analog circuit block in the plurality of analog circuit blocks to at least a first portion of image sensor pixels in the selected group; and

with the configurable interconnect circuitry, selectively routing the pixel output signals from the first portion of image sensor pixels to the first analog circuit block.

10. THe method defined in claim 9 , wherein simultaneously accessing each image sensor pixel in the selected one of the respective groups further comprises:

with the configurable interconnect circuitry, selectively routing the pixel control signals from a second analog circuit block in the plurality of analog circuit blocks to at least a second portion of image sensor pixels in the selected group; and

with the configurable interconnect circuitry, selectively routing the pixel output signals from the second portion of image sensor pixels to the second analog circuit block.

Assignments (5)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 27, 2015
From: KIRSCH, GRAHAM
To: APTINA IMAGING CORPORATION
Reel/Frame 035047/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 27, 2015
From: APTINA IMAGING CORPORATION
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 035047/0088 →