Silicon carbide semiconductor device

1. A silicon carbide semiconductor device comprising:

a silicon carbide layer including a first main surface and a second main surface located opposite to said first main surface, said silicon carbide layer having a first conductivity type;

a body region disposed within said silicon carbide layer, said body region having a second conductivity type different from said first conductivity type;

a source region disposed within said body region so as to be in contact with said first main surface of said silicon carbide layer, said source region having said first conductivity type;

a gate insulating film disposed so as to cover a surface of at least a portion of said body region which lies between said source region and said silicon carbide layer;

a gate electrode in contact with said gate insulating film;

a source electrode disposed so as to be electrically connected to said body region and said source region;

a first impurity region disposed within said silicon carbide layer and away from said body region, across said body region from said gate electrode in a direction along said first main surface of said silicon carbide layer, said first impurity region having said second conductivity type; and

a second impurity region disposed within said silicon carbide layer so as to connect said body region and said first impurity region to each other, said second impurity region having said second conductivity type,

an impurity concentration in said second impurity region being equal to or higher than an impurity concentration in said silicon carbide layer and equal to or lower than a lower limit of an impurity concentration in said body region.

2. The silicon carbide semiconductor device according to claim 1 , wherein

the impurity concentration in said second impurity region is lower than the lower limit of the impurity concentration in said body region.

3. The silicon carbide semiconductor device according to claim 1 , wherein

the impurity concentration in said second impurity region is not less than 1×10 14 cm −3 and less than 5×10 17 cm −3 .

4. The silicon carbide semiconductor device according to claim 3 , wherein

the impurity concentration in said second impurity region is not less than 1×10 16 cm −3 and less than 5×10 17 cm −3 .

5. The silicon carbide semiconductor device according to claim 1 , wherein

the length of said second impurity region along said first main surface of said silicon carbide layer from said body region to said first impurity region is equal to or greater than ⅓ of the thickness of said silicon carbide layer.

6. The silicon carbide semiconductor device according to claim 1 , wherein

said first main surface of said silicon carbide layer is provided with a trench, said trench including a side portion extending through said source region and said body region to reach said silicon carbide layer,

said gate insulating film is in contact with said side portion of said trench, and

said gate electrode is in contact with said gate insulating film within said trench.

7. The silicon carbide semiconductor device according to claim 1 , wherein

said first main surface of said silicon carbide layer includes

a first surface in contact with said source region,

a second surface connected to said first surface and inclined with respect to said first surface so as to extend toward said second main surface of said silicon carbide layer, and

a third surface connected to said second surface and being in contact with said first impurity region.

8. The silicon carbide semiconductor device according to claim 1 , wherein

said first conductivity type is n type, and

said second conductivity type is p type.