Multilevel contact to a 3D memory array and method of making thereof

1. A method of fabricating a multilevel structure, comprising:

forming a stack including an alternating plurality of electrically conductive layers and electrically insulating layers over a substrate;

forming a recessed region through the stack, wherein top surfaces of a first set of electrically conductive layers located at different levels are physically exposed within the recessed region;

forming a first electrically conductive spacer directly on the top surfaces of the first set of electrically conductive layers within the recessed region; and

forming at least one trench isolation structure extending through the stack, wherein the at least one trench isolation structure divides the first electrically conductive spacer into a plurality of electrically conductive via connections.

2. The method of claim 1 , wherein the plurality of electrically conducive via connections is formed with top surfaces located within a same horizontal plane, and with bottom surfaces contacting a respective electrically conductive layer located at different levels.

3. The method of claim 1 , wherein the recessed region is formed by sequentially performing multiple combinations of a lithographic patterning process and an etch process employing different patterns for opening in each respective photoresist layer, wherein a depth of recess in the recessed region differs depending on different overlap patterns among the openings of different photoresist layers.

4. The method of claim 3 , wherein each etch process within the multiple combinations through a different number of electrically insulating layers.

5. The method of claim 4 , wherein numbers of electrically insulating layers that are etched through per etch process within the multiple combinations include at least 1, 2, and 4.

6. The method of claim 1 , further comprising forming a first stepped dielectric spacer on the top surfaces of the first set of electrically conductive layers and on a sidewall of the recessed region, wherein the first electrically conductive spacer is formed on an outer sidewall of the first stepped dielectric spacer.

7. The method of claim 6 , wherein the first stepped dielectric spacer is formed by:

forming a first conformal dielectric layer over the stack and on a sidewall of the recessed region; and

removing horizontal portions of the first conformal dielectric layer by an anisotropic etch, wherein a remaining portion of the first conformal dielectric layer constitutes the first stepped dielectric spacer.

8. The method of claim 7 , wherein the first stepped dielectric spacer has a plurality of top surfaces that are vertically offset among one another.

9. The method of claim 6 , further comprising forming a second stepped dielectric spacer on top surfaces of a second set of electrically conductive layers located at different levels that are present below the bottommost surface of the first stepped dielectric spacer, and on sidewalls of the first electrically conductive spacer.

10. The method of claim 9 , further comprising forming a second electrically conductive spacer on the top surfaces of the second set of electrically conductive layers, and on sidewalls of the second stepped dielectric spacer.

11. The method of claim 1 , wherein physically exposed surfaces of the first set of electrically conductive layers form a set of stepped surfaces prior to formation of the first electrically conductive spacer.

12. The method of claim 11 , further comprising recessing portions of the set of stepped surfaces that do not underlie the first electrically conductive spacer to form another set of stepped surfaces including top surfaces of a second set of electrically conductive layers that underlie the first set of electrically conductive layers.

13. The method of claim 12 , further comprising forming a first stepped dielectric spacer on top surfaces of the first set of electrically conductive layers and on a sidewall of the recessed region, wherein the first electrically conductive spacer is formed on an outer sidewall of the first stepped dielectric spacer.

14. The method of claim 13 , further comprising forming a second electrically conductive spacer on the top surfaces of the second set of electrically conductive layers.

15. The method of claim 1 , further comprising forming a dielectric material portion over the first electrically conductive spacer, wherein each of the at least one trench isolation structure is formed through a portion of the dielectric material portion.

16. The method of claim 1 , wherein the plurality of electrically conductive via connections includes an m ×n two-dimensional array of electrically conductive via connections that are spaced from one another by a plurality of trench isolation structures along one horizontal direction and by a set of dielectric spacers having a same composition and a same thickness along another direction, wherein m is an integer greater than 1, and n is an integer greater than 2.

17. The method of claim 16 , wherein each electrically conductive via connection within the m ×n two-dimensional array of electrically conductive via connections contacts a top surface of a respective electrically conductive layer located at levels that are different from one another.

18. The method of claim 1 , further comprising forming a device on the substrate, wherein:

the device comprises a vertical NAND device; and

at least one of the plurality electrically conductive layers in the stack comprises or is electrically connected to a word line of the NAND device.

19. The method of claim 18 , wherein:

the device region comprises:

a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate;

a plurality of charge storage regions, each charge storage region located adjacent to a respective one of the plurality of semiconductor channels; and

a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate;

the plurality of control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level; and

a plurality of electrically conductive layers in the stack comprises, or is in electrical contact with, the plurality of control gate electrode and extends from the device region to a contact region including the plurality of electrically conductive via connections.

20. The method of claim 18 , wherein:

the device comprises a three-dimensional ReRAM device; and

at least one of the electrically conductive layers in the stack comprises, or is electrically connected to, an electrode of the ReRAM device.

21. The method of claim 1 , wherein:

bottom surfaces of the first electrically conductive spacer physically contact the top surfaces of the first set of electrically conductive layers; and

the bottom surfaces of the first electrically conductive spacer are vertically spaced from a top surface of the substrate by different distances.

22. The method of claim 1 , wherein the at least one trench isolation structure physically contacts remaining portions of the first electrically conductive spacer upon formation of the at least one trench isolation structure.

23. The method of claim 1 , further comprising forming at least one trench through the first electrically conductive spacer and through a portion of the stack employing an anisotropic etch process that etches materials of the first electrically conductive spacer and the stack.

24. The method of claim 23 , further comprising depositing a dielectric material directly on sidewalls of the electrically conductive layers and sidewalls of remaining portions of the first electrically conductive spacer, wherein each of the at least one trench isolation structure comprises a portion of the deposited dielectric material.

25. The method of claim 1 , further comprising anisotropically etching portions of the first electrically conductive spacer, wherein each remaining portion of the first electrically conductive spacer after the anisotropic etch constitutes the plurality of electrically conductive via connections.

26. The method of claim 1 , wherein each of the plurality electrically conductive via connections extends vertically from a horizontal plane located above a topmost electrically conductive layer within the stack to a top surface of a respective electrically conductive layer within the stack.

27. The method of claim 1 , wherein the first electrically conductive spacer has multiple bottom surfaces located at different levels and contacting respective top surfaces of a subset of the electrically conductive layers within the stack.

28. A method of fabricating a multilevel structure, comprising:

forming a stack including an alternating plurality of electrically conductive layers and electrically insulating layers over a substrate;

forming a recessed region through the stack, wherein top surfaces of a first set of electrically conductive layers located at different levels are physically exposed within the recessed region;

forming a first conformal layer of electrically conductive material directly on a first sidewall of a first electrically insulating layer and directly on an exposed portion of a first electrically conductive layer that underlies the first electrically insulating layer;

etching horizontal portions of the first conformal layer to form a first electrically conductive spacer adjacent to the first sidewall and to physically expose a portion of a second electrically insulating layer located under the first electrically conductive layer, wherein the exposed portion extends laterally past the first electrically conductive spacer;

forming a first conformal insulating layer of an electrically insulating material over the first electrically conductive spacer and the exposed portion of the second electrically insulating layer; and

etching horizontal portions of the first conformal insulating layer to form a first electrically insulating sidewall spacer adjacent to the first electrically conductive spacer, and to expose a portion of a second electrically conductive layer underlying the second electrically insulating layer.

29. The method of claim 28 , wherein:

bottom surfaces of the first electrically conductive spacer physically contact the top surfaces of the first set of electrically conductive layers; and

the bottom surfaces of the first electrically conductive spacer are vertically spaced from a top surface of the substrate by different distances.

30. The method of claim 28 , wherein the at least one trench isolation structure physically contacts remaining portions of the first electrically conductive spacer upon formation of the at least one trench isolation structure.

31. The method of claim 28 , further comprising further comprising forming at least one trench through the first electrically conductive spacer and through a portion of the stack employing an anisotropic etch process that etches materials of the first electrically conductive spacer and the stack.

32. The method of claim 31 , further comprising depositing a dielectric material directly on sidewalls of the electrically conductive layers and sidewalls of remaining portions of the first electrically conductive spacer, wherein each of the at least one trench isolation structure comprises a portion of the deposited dielectric material.

33. The method of claim 28 , further comprising anisotropically etching portions of the first electrically conductive spacer, wherein each remaining portion of the first electrically conductive spacer after the anisotropic etch constitutes the plurality of electrically conductive via connections.

34. The method of claim 28 , wherein each of the plurality electrically conductive via connections extends vertically from a horizontal plane located above a topmost electrically conductive layer within the stack to a top surface of a respective electrically conductive layer within the stack.

35. The method of claim 28 , wherein the first electrically conductive spacer has multiple bottom surfaces located at different levels and contacting respective top surfaces of a subset of the electrically conductive layers within the stack.